{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,19]],"date-time":"2026-03-19T01:43:43Z","timestamp":1773884623804,"version":"3.50.1"},"reference-count":21,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,9]]},"DOI":"10.1109\/fpl.2015.7293982","type":"proceedings-article","created":{"date-parts":[[2015,10,8]],"date-time":"2015-10-08T17:58:09Z","timestamp":1444327089000},"page":"1-4","source":"Crossref","is-referenced-by-count":4,"title":["Accurate power analysis for near-V<inf>t<\/inf> RRAM-based FPGA"],"prefix":"10.1109","author":[{"given":"Xifan","family":"Tang","sequence":"first","affiliation":[]},{"given":"Pierre-Emmanuel","family":"Gaillardon","sequence":"additional","affiliation":[]},{"given":"Giovanni","family":"De Micheli","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1147\/rd.524.0449"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2012.2190369"},{"key":"ref12","year":"2015","journal-title":"Stratix 10 Advance Information Brief"},{"key":"ref13","year":"2015","journal-title":"Xilinx Virtex-7 User Guide DS180 (v1 17)"},{"key":"ref14","first-page":"135","article-title":"Improving FPGA Performance and Area Using an Adaptive Logic Module","author":"hutton","year":"2004","journal-title":"FPL"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2334891"},{"key":"ref16","year":"0"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645511"},{"key":"ref18","year":"2008","journal-title":"Altera Corporation Stratix IV Device Handbook"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145708"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2259512"},{"key":"ref3","first-page":"2023","article-title":"FPGA Based on Integration of CMOS and RRAM","volume":"19","author":"tanachutiwat","year":"2010","journal-title":"TVLSI"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2014.7082777"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2012.6379012"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2012.6412139"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1059876.1059881"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2010.5681535"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2012.6339206"},{"key":"ref9","first-page":"1712","article-title":"Power Modeling and Characteristics of Field Programmable Gate Arrays","volume":"24","author":"li","year":"2005","journal-title":"TCAD"},{"key":"ref20","author":"berkeley","year":"0","journal-title":"ABC A System for Sequential Synthesis and Verification"},{"key":"ref21","author":"yang","year":"1991","journal-title":"Logic synthesis and optimization benchmarks user guide version 3 0 MCNC"}],"event":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","location":"London, United Kingdom","start":{"date-parts":[[2015,9,2]]},"end":{"date-parts":[[2015,9,4]]}},"container-title":["2015 25th International Conference on Field Programmable Logic and Applications (FPL)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7284611\/7293744\/07293982.pdf?arnumber=7293982","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T18:33:43Z","timestamp":1490380423000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7293982\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,9]]},"references-count":21,"URL":"https:\/\/doi.org\/10.1109\/fpl.2015.7293982","relation":{},"subject":[],"published":{"date-parts":[[2015,9]]}}}