{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T01:24:29Z","timestamp":1725413069168},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,9]]},"DOI":"10.1109\/fpl.2015.7294000","type":"proceedings-article","created":{"date-parts":[[2015,10,8]],"date-time":"2015-10-08T21:58:09Z","timestamp":1444341489000},"page":"1-4","source":"Crossref","is-referenced-by-count":0,"title":["UniStream: A unified stream architecture combining configuration and data processing"],"prefix":"10.1109","author":[{"family":"Jian Yan","sequence":"first","affiliation":[]},{"family":"Jifang Jin","sequence":"additional","affiliation":[]},{"given":"Ying","family":"Wang","sequence":"additional","affiliation":[]},{"family":"Xuegong Zhou","sequence":"additional","affiliation":[]},{"given":"Philip","family":"Leong","sequence":"additional","affiliation":[]},{"family":"Lingli Wang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2068716.2068722"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2009.5272463"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2011.48"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20050131"},{"journal-title":"Opencores","article-title":"AES Project","year":"0","key":"ref14"},{"journal-title":"Opencores","article-title":"DES Project","year":"0","key":"ref15"},{"journal-title":"Opencores","article-title":"Pipelined DCT\/IDCT","year":"0","key":"ref16"},{"key":"ref4","first-page":"837","article-title":"VAPRES: A Virtual Architecture for Partially Reconfigurable Embedded Systems","author":"berrocal","year":"2010","journal-title":"Design Automation & Test in Europe Conference & Exhibition (DATE)"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.72"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1155\/2011\/439072"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2012.6412113"},{"key":"ref8","first-page":"253","article-title":"FaRM: Fast Reconfiguration Manager for Reducing Reconfiguration Time Overhead on FPGA","author":"duhem","year":"2011","journal-title":"Reconfigurable Computing Architectures Tools and Applications ARC 2011 International Symposium on"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2011.139"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2012.6412147"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt.2011.0033"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2231101"}],"event":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","start":{"date-parts":[[2015,9,2]]},"location":"London, United Kingdom","end":{"date-parts":[[2015,9,4]]}},"container-title":["2015 25th International Conference on Field Programmable Logic and Applications (FPL)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7284611\/7293744\/07294000.pdf?arnumber=7294000","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T22:22:21Z","timestamp":1490394141000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7294000\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,9]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/fpl.2015.7294000","relation":{},"subject":[],"published":{"date-parts":[[2015,9]]}}}