{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T06:34:25Z","timestamp":1729665265246,"version":"3.28.0"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,9]]},"DOI":"10.1109\/fpl.2015.7294005","type":"proceedings-article","created":{"date-parts":[[2015,10,8]],"date-time":"2015-10-08T17:58:09Z","timestamp":1444327089000},"page":"1-4","source":"Crossref","is-referenced-by-count":0,"title":["Fast FPGA system for microarchitecture optimization on synthesizable modern processor design"],"prefix":"10.1109","author":[{"family":"Libo Huang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Yongwen Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Qiang Dou","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Chengyi Zhang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Caixia Sun","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Chao Xu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1723112.1723116"},{"journal-title":"SPEC","year":"0","key":"ref11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2002.1028478"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1508128.1508160"},{"journal-title":"Xilinx Vivado Design Suite User Guide Hierarchical Design","year":"2014","key":"ref14"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2012.6189225"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145720"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1723112.1723122"},{"key":"ref5","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-031-01727-8","author":"eeckhout","year":"2010","journal-title":"Computer Architecture Performance Evaluation Methods"},{"key":"ref8","first-page":"61","article-title":"SCOORE: Santa Cruz Out-of-Order RISC Engine, FPGA Design Issues","author":"mart\u00ednez","year":"2006","journal-title":"WARP '06"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1216919.1216927"},{"key":"ref2","first-page":"67","article-title":"Modeling, Validation, and Co-design of IBM Blue Gene\/Q: Tools and Examples","volume":"57","author":"asaad","year":"2013","journal-title":"IBM J Res Dev"},{"journal-title":"ARM Prototyping","year":"0","key":"ref1"},{"journal-title":"Xilinx Timing Closure 6 1i","year":"2008","author":"rhett","key":"ref9"}],"event":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","start":{"date-parts":[[2015,9,2]]},"location":"London, United Kingdom","end":{"date-parts":[[2015,9,4]]}},"container-title":["2015 25th International Conference on Field Programmable Logic and Applications (FPL)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7284611\/7293744\/07294005.pdf?arnumber=7294005","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,8,14]],"date-time":"2023-08-14T23:23:58Z","timestamp":1692055438000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7294005\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,9]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/fpl.2015.7294005","relation":{},"subject":[],"published":{"date-parts":[[2015,9]]}}}