{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:58:24Z","timestamp":1759147104484,"version":"3.41.0"},"reference-count":30,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,9]]},"DOI":"10.1109\/fpl.2015.7294013","type":"proceedings-article","created":{"date-parts":[[2015,10,8]],"date-time":"2015-10-08T21:58:09Z","timestamp":1444341489000},"page":"1-8","source":"Crossref","is-referenced-by-count":15,"title":["Fine-tuning CLB placement to speed up reconfigurations in NVM-based FPGAs"],"prefix":"10.1109","author":[{"given":"Yuan","family":"Xue","sequence":"first","affiliation":[]},{"given":"Patrick","family":"Cronin","sequence":"additional","affiliation":[]},{"given":"Chengmo","family":"Yang","sequence":"additional","affiliation":[]},{"given":"Jingtong","family":"Hu","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1989.100747"},{"key":"ref10","doi-asserted-by":"crossref","DOI":"10.1561\/1000000005","article-title":"FPGA architecture: survey and challenges","volume":"2","author":"kuon","year":"2008","journal-title":"Foundations and Trends in Electronic Design Automation"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2617593"},{"journal-title":"Partial Reconfiguration User Guide Xilinx","year":"2011","key":"ref12"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429491"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2007.4380744"},{"key":"ref15","first-page":"76","article-title":"Reconfigurable multi-functioning logic structures: a case study of MMX\/floating-point unit design","author":"yang","year":"1999","journal-title":"IEEE Computer Society VLSI Workshop"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2006.1639611"},{"article-title":"Architectures and algorithms for field programmable gate arrays with embedded memory","year":"1997","author":"wilton","key":"ref17"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2007.370385"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2011.5770732"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2015.7059056"},{"journal-title":"Understanding Soft and Firm Errors in Semiconductor Devices","year":"2002","key":"ref4"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2014.6974691"},{"key":"ref3","article-title":"Consequences and categories of SRAM FPGA configuration SEUs","author":"graham","year":"2003","journal-title":"Los Alamos National Laboratory and Xilinx"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2010.5724454"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1002\/nav.3800020109"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/NVSMW.2007.4290569"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1840845.1840857"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICICDT.2006.220782"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.909795"},{"journal-title":"International Technology Roadmap for Semiconductors","year":"2013","key":"ref9"},{"key":"ref1","article-title":"A low active leakage and high reliability phase change memory (PCM) based nonvolatile FPGA storage element","volume":"61","author":"huang","year":"2014","journal-title":"IEEE Transactions on Circuits and Systems"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1508128.1508131"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2006.311255"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687546"},{"key":"ref24","first-page":"1","article-title":"Leveraging microarchitectural side channel information to efficiently enhance program control flow integrity","author":"khouzani","year":"2014"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/2627369.2627667"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5456923"},{"key":"ref25","first-page":"508","article-title":"Improving performance and lifetime of DRAM-PCM hybrid main memory through a proactive page allocation strategy","author":"liu","year":"2015","journal-title":"Asia and South Pacific Design Automation Conference (ASP-DAC)"}],"event":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","start":{"date-parts":[[2015,9,2]]},"location":"London, United Kingdom","end":{"date-parts":[[2015,9,4]]}},"container-title":["2015 25th International Conference on Field Programmable Logic and Applications (FPL)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7284611\/7293744\/07294013.pdf?arnumber=7294013","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,30]],"date-time":"2025-05-30T23:48:00Z","timestamp":1748648880000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7294013\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,9]]},"references-count":30,"URL":"https:\/\/doi.org\/10.1109\/fpl.2015.7294013","relation":{},"subject":[],"published":{"date-parts":[[2015,9]]}}}