{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T06:24:28Z","timestamp":1729664668921,"version":"3.28.0"},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,9]]},"DOI":"10.1109\/fpl.2015.7294015","type":"proceedings-article","created":{"date-parts":[[2015,10,8]],"date-time":"2015-10-08T17:58:09Z","timestamp":1444327089000},"page":"1-6","source":"Crossref","is-referenced-by-count":3,"title":["SPINE: From C loop-nests to highly efficient accelerators using Algorithmic Species"],"prefix":"10.1109","author":[{"given":"Mark","family":"Wijtvliet","sequence":"first","affiliation":[]},{"given":"Shakith","family":"Fernando","sequence":"additional","affiliation":[]},{"given":"Henk","family":"Corporaal","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2012.6339272"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.825848"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/SASP.2009.5226333"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2015.0015"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MuCoCoS.2013.6633604"},{"journal-title":"The OpenCV Reference Manual Release 2 4 9 0 Itseez","year":"2014","key":"ref15"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/RSP.2013.6683970"},{"key":"ref4","first-page":"5","article-title":"MyHDL: A Python-based Hardware Description Language","volume":"2004","author":"decaluwe","year":"2004","journal-title":"Linux J"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2665079"},{"key":"ref6","first-page":"75","article-title":"systemc - a modeling platform supporting multiple design abstractions","author":"panda","year":"2001","journal-title":"International Symposium on System Synthesis (IEEE Cat No 01EX526) ISSS-01"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"175","DOI":"10.1109\/FPGA.1998.707895","article-title":"JHDL-an HDL for reconfigurable systems","author":"bellows","year":"1998","journal-title":"FPGAs for Custom Computing Machines 1998 Proceedings IEEE Symposium on"},{"year":"2008","key":"ref8","article-title":"Catapult c synthesis"},{"key":"ref7","article-title":"Vivado design suite","author":"feist","year":"2012","journal-title":"White Paper"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICDSC.2013.6778245"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2014.6853195"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2435264.2435266"}],"event":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","start":{"date-parts":[[2015,9,2]]},"location":"London, United Kingdom","end":{"date-parts":[[2015,9,4]]}},"container-title":["2015 25th International Conference on Field Programmable Logic and Applications (FPL)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7284611\/7293744\/07294015.pdf?arnumber=7294015","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,23]],"date-time":"2017-06-23T17:00:21Z","timestamp":1498237221000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7294015\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,9]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/fpl.2015.7294015","relation":{},"subject":[],"published":{"date-parts":[[2015,9]]}}}