{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,27]],"date-time":"2026-01-27T18:25:26Z","timestamp":1769538326137,"version":"3.49.0"},"reference-count":46,"publisher":"IEEE","license":[{"start":{"date-parts":[[2015,9,1]],"date-time":"2015-09-01T00:00:00Z","timestamp":1441065600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2015,9,1]],"date-time":"2015-09-01T00:00:00Z","timestamp":1441065600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,9]]},"DOI":"10.1109\/fpl.2015.7294022","type":"proceedings-article","created":{"date-parts":[[2015,10,8]],"date-time":"2015-10-08T17:58:09Z","timestamp":1444327089000},"page":"1-8","source":"Crossref","is-referenced-by-count":8,"title":["Enabling seamless execution on hybrid CPU\/FPGA systems: Challenges &amp; directions"],"prefix":"10.1109","author":[{"given":"Meena","family":"Belwal","sequence":"first","affiliation":[{"name":"Department of Computer Science and Engineering, Amrita School of Engineering, Bangalore, Amrita Vishwavidya Peetham (Amrita University), India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Madhura","family":"Purnaprajna","sequence":"additional","affiliation":[{"name":"Department of Computer Science and Engineering, Amrita School of Engineering, Bangalore, Amrita Vishwavidya Peetham (Amrita University), India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Sudarshan TSB","sequence":"additional","affiliation":[{"name":"Department of Computer Science and Engineering, Amrita School of Engineering, Bangalore, Amrita Vishwavidya Peetham (Amrita University), India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2008.240"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2014.02.008"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/2700082"},{"key":"ref32","article-title":"A Coarse-Grain FPGA Overlay for Executing Data Flow Graphs","year":"0"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/2435264.2435296"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/1878961.1878966"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/2380445.2380491"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/544536.544540"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2011.17"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/1046192.1046247"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2010.28"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1145\/2086696.2086712"},{"key":"ref11","article-title":"Celoxica, Handel-C Language Reference Manual for DK2.0, Document RM-1003&#x2013;4.0","year":"2003"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2008.4629927"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20045086"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950423"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1007\/s10617-012-9096-8"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2009.69"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2006.45"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1155\/2013\/789134"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1016\/j.parco.2012.05.001"},{"key":"ref28","article-title":"VectorBlox","year":"2015"},{"key":"ref4","article-title":"Operating system interfaces: Bridging the gap between CPU and FPGA accelerators","volume":"48","author":"kelm","year":"2007","journal-title":"Intl Symp on FPGAs"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1155\/2011\/514581"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"77","DOI":"10.1109\/FPL.2008.4629911","article-title":"How fast is an FPGA in image processing?","author":"saegusa","year":"2008","journal-title":"Field Programmable Logic and Applications 2008 FPL 2008 International Conference on"},{"key":"ref6","article-title":"OpenCL","year":"2015"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2014.6927456"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1596532.1596540"},{"key":"ref8","article-title":"Altera SDK for OpenCL","year":"2015"},{"key":"ref7","article-title":"XeonPhi","year":"2015"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2007.4380764"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2011.19"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2011.64"},{"key":"ref46","article-title":"AMD Accelerated Processing Unit","year":"2012"},{"key":"ref20","first-page":"195","article-title":"Operating systems for FPGA based computers and their memory management","author":"danne","year":"2004","journal-title":"Organic and Pervasive Computing Workshop (ARCS' &#x2018;04)"},{"key":"ref45","article-title":"Unified Memory in CUDA 6","year":"2013"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/1086297.1086325"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950419"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1145\/2581122.2544163"},{"key":"ref24","doi-asserted-by":"crossref","first-page":"659","DOI":"10.1145\/996566.1142986","article-title":"Warp Processors","author":"lysecky","year":"2004","journal-title":"Proceedings of the 41st Annual Design Automation Conference"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429513"},{"key":"ref23","first-page":"29:1","article-title":"A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses","volume":"7","author":"paulino","year":"2054","journal-title":"ACM Trans Reconfigurable Technol Syst"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2010.36"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/1970353.1970365"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/SASP.2009.5226333"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2008.4484843"}],"event":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","location":"London, UK","start":{"date-parts":[[2015,9,2]]},"end":{"date-parts":[[2015,9,4]]}},"container-title":["2015 25th International Conference on Field Programmable Logic and Applications (FPL)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7284611\/7293744\/07294022.pdf?arnumber=7294022","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,1,27]],"date-time":"2026-01-27T05:13:06Z","timestamp":1769490786000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/7294022\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,9]]},"references-count":46,"URL":"https:\/\/doi.org\/10.1109\/fpl.2015.7294022","relation":{},"subject":[],"published":{"date-parts":[[2015,9]]}}}