{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,1]],"date-time":"2025-11-01T11:00:24Z","timestamp":1761994824152,"version":"build-2065373602"},"reference-count":54,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,8]]},"DOI":"10.1109\/fpl.2016.7577380","type":"proceedings-article","created":{"date-parts":[[2016,9,29]],"date-time":"2016-09-29T22:11:15Z","timestamp":1475187075000},"page":"1-12","source":"Crossref","is-referenced-by-count":11,"title":["Survey of domain-specific languages for FPGA computing"],"prefix":"10.1109","author":[{"given":"Nachiket","family":"Kapre","sequence":"first","affiliation":[]},{"given":"Samuel","family":"Bayliss","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref39","DOI":"10.1145\/1118890.1118892"},{"key":"ref38","article-title":"The Next IC Design Methodology Transition Is Long Overdue","author":"meredith","year":"2010","journal-title":"Accellera Systems Initiative"},{"doi-asserted-by":"publisher","key":"ref33","DOI":"10.1145\/354871.354874"},{"doi-asserted-by":"publisher","key":"ref32","DOI":"10.1109\/FPT.2011.6132678"},{"doi-asserted-by":"publisher","key":"ref31","DOI":"10.1109\/FCCM.2009.14"},{"doi-asserted-by":"publisher","key":"ref30","DOI":"10.1109\/ICASSP.2001.941073"},{"doi-asserted-by":"publisher","key":"ref37","DOI":"10.1109\/FCCM.2012.23"},{"doi-asserted-by":"publisher","key":"ref36","DOI":"10.1109\/CICC.2002.1012760"},{"doi-asserted-by":"publisher","key":"ref35","DOI":"10.1109\/FCCM.2011.17"},{"doi-asserted-by":"publisher","key":"ref34","DOI":"10.1145\/996566.996811"},{"year":"2004","author":"iman","journal-title":"The e Hardware Verification Language","key":"ref28"},{"key":"ref27","doi-asserted-by":"crossref","first-page":"111","DOI":"10.1109\/FPGA.2002.1106666","article-title":"Assisting network intrusion detection with reconfigurable hardware","author":"hutchings","year":"2002","journal-title":"Field-Programmable Custom Computing Machines 2002 Proceedings 10th Annual IEEE Symposium of"},{"year":"0","article-title":"MATLAB HDL Coder","key":"ref29"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1109\/ANCS.2011.12"},{"year":"2012","journal-title":"IEEE Standard for SystemVerilog - Unified Hardware Design Specification and Verification Language","key":"ref1"},{"doi-asserted-by":"publisher","key":"ref20","DOI":"10.1109\/FCCM.2006.45"},{"doi-asserted-by":"publisher","key":"ref22","DOI":"10.1109\/FPL.2014.6927454"},{"doi-asserted-by":"publisher","key":"ref21","DOI":"10.1109\/FCCM.2012.18"},{"doi-asserted-by":"publisher","key":"ref24","DOI":"10.1145\/1323548.1323579"},{"doi-asserted-by":"publisher","key":"ref23","DOI":"10.1145\/1190215.1190269"},{"key":"ref26","article-title":"Using MATLAB to Create IP for System Generator for DSP","author":"hill","year":"2006","journal-title":"tech rep Xilinx Inc"},{"key":"ref25","article-title":"AccelDSP IP Explorer","author":"hill","year":"2006","journal-title":"tech rep Xilinx Inc"},{"doi-asserted-by":"publisher","key":"ref50","DOI":"10.1016\/S0164-1212(00)00089-3"},{"doi-asserted-by":"publisher","key":"ref51","DOI":"10.1145\/1950413.1950425"},{"doi-asserted-by":"publisher","key":"ref54","DOI":"10.1145\/352029.352035"},{"year":"2013","journal-title":"OpenSPL Revealing the Power of Spatial Computing","article-title":"The OpenSPL Consortium","key":"ref53"},{"key":"ref52","first-page":"609","article-title":"OptiML: an implicitly parallel domain-specific language for machine learning","author":"sujeeth","year":"2011","journal-title":"Proceedings of the 28th International Conference on Machine Learning (ICML-11)"},{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1145\/2656877.2656890"},{"key":"ref11","article-title":"Domain-Specific Programming of Very High Speed Packet Processing","author":"brebner","year":"0","journal-title":"Technical Report"},{"doi-asserted-by":"publisher","key":"ref40","DOI":"10.1145\/1323548.1323571"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1109\/FPT.2009.5377604"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1145\/2514740"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.1007\/3-540-44614-1_65"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1145\/1950413.1950435"},{"doi-asserted-by":"publisher","key":"ref16","DOI":"10.1145\/2435264.2435267"},{"doi-asserted-by":"publisher","key":"ref17","DOI":"10.1109\/TCAD.2011.2110592"},{"doi-asserted-by":"publisher","key":"ref18","DOI":"10.1109\/FPL.2009.5272553"},{"doi-asserted-by":"publisher","key":"ref19","DOI":"10.1145\/2019583.2019584"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1145\/2436256.2436271"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1145\/2228360.2228584"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1109\/FPGA.1994.315599"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"175","DOI":"10.1109\/FPGA.1998.707895","article-title":"JHDL-an HDL for reconfigurable systems","author":"bellows","year":"1998","journal-title":"FPGAs for Custom Computing Machines 1998 Proceedings IEEE Symposium on"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1145\/291251.289440"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1145\/1556444.1556449"},{"doi-asserted-by":"publisher","key":"ref49","DOI":"10.1049\/ic:19951042"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1109\/FCCM.2010.51"},{"doi-asserted-by":"publisher","key":"ref46","DOI":"10.1109\/FCCM.2014.15"},{"doi-asserted-by":"publisher","key":"ref45","DOI":"10.1145\/1065579.1065703"},{"doi-asserted-by":"publisher","key":"ref48","DOI":"10.1145\/1872007.1872052"},{"doi-asserted-by":"publisher","key":"ref47","DOI":"10.1145\/2082156.2082172"},{"doi-asserted-by":"publisher","key":"ref42","DOI":"10.1145\/1807167.1807307"},{"doi-asserted-by":"publisher","key":"ref41","DOI":"10.14778\/1687627.1687654"},{"year":"0","article-title":"NetFPGA Wiki","key":"ref44"},{"year":"0","article-title":"NI LabVIEW","key":"ref43"}],"event":{"name":"2016 26th International Conference on Field Programmable Logic and Applications (FPL)","start":{"date-parts":[[2016,8,29]]},"location":"Lausanne, Switzerland","end":{"date-parts":[[2016,9,2]]}},"container-title":["2016 26th International Conference on Field Programmable Logic and Applications (FPL)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7573873\/7577295\/07577380.pdf?arnumber=7577380","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,25]],"date-time":"2017-06-25T00:00:18Z","timestamp":1498348818000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7577380\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,8]]},"references-count":54,"URL":"https:\/\/doi.org\/10.1109\/fpl.2016.7577380","relation":{},"subject":[],"published":{"date-parts":[[2016,8]]}}}