{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,27]],"date-time":"2026-03-27T06:58:12Z","timestamp":1774594692085,"version":"3.50.1"},"reference-count":46,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,9,1]],"date-time":"2025-09-01T00:00:00Z","timestamp":1756684800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,9,1]],"date-time":"2025-09-01T00:00:00Z","timestamp":1756684800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["2303626"],"award-info":[{"award-number":["2303626"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001475","name":"Nanyang Technological University","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100001475","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,9,1]]},"DOI":"10.1109\/fpl68686.2025.00016","type":"proceedings-article","created":{"date-parts":[[2026,3,26]],"date-time":"2026-03-26T19:48:24Z","timestamp":1774554504000},"page":"27-36","source":"Crossref","is-referenced-by-count":0,"title":["Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage"],"prefix":"10.1109","author":[{"given":"Junius","family":"Pun","sequence":"first","affiliation":[{"name":"Nanyang Technological University"}]},{"given":"Xilai","family":"Dai","sequence":"additional","affiliation":[{"name":"Cornell University"}]},{"given":"Grace","family":"Zgheib","sequence":"additional","affiliation":[{"name":"Altera"}]},{"given":"Mahesh A.","family":"Iyer","sequence":"additional","affiliation":[{"name":"Altera"}]},{"given":"Andrew","family":"Boutros","sequence":"additional","affiliation":[{"name":"University of Waterloo"}]},{"given":"Vaughn","family":"Betz","sequence":"additional","affiliation":[{"name":"University of Toronto"}]},{"given":"Mohamed S.","family":"Abdelfattah","sequence":"additional","affiliation":[{"name":"Cornell University"}]}],"member":"263","reference":[{"key":"ref1","article-title":"Azure accelerated networking: SmartNICs in the public cloud","volume-title":"Proceedings of the 15th USENIX Symposium on Networked Systems Design and Implementation (NSDI)","author":"Firestone","year":"2018"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021742"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2016.7929186"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/fccm57271.2023.00047"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/jiot.2023.3333532"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM60383.2024.00011"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2018.00077"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3626202.3637562"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3490422.3502360"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO61859.2024.00040"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3431920.3439293"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/3431920.3439282"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/3289602.3293906"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1088\/1748-0221\/13\/07\/P07027"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2019.00014"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ICFPT59805.2023.00012"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/3359983"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/FPL64840.2024.00030"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/3289602.3293912"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/3373087.3375303"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2018.00091"},{"key":"ref22","volume-title":"Intel Arria Native Fixed Point DSP IP Core User Guide: Functional Description, Intel Corporation"},{"key":"ref23","volume-title":"Versal Adaptive SoC Technical Reference Manual (AM011) Digital Signal Processor, AMD","year":"2025"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2018.00014"},{"key":"ref25","article-title":"CoMeFa: Deploying compute-in-memory on FPGAs for deep learning acceleration","volume-title":"Proceedings of the 30th IEEE Annual International Symposium on FieldProgrammable Custom Computing Machines (FCCM)","author":"Arora","year":"2022"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM57271.2023.00015"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ICFPT59805.2023.00013"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/3289602.3293927"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8715262"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2008.4483927"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2014.6927468"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/3645097"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/3393668"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2013.6718327"},{"key":"ref35","article-title":"VTR 9: Open-source CAD for fabric and beyond FPGA architecture exploration","author":"Elgammal","year":"2025","journal-title":"ACM Transactions on Reconfigurable Technology and Systems (TRETS)"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2023.3272582"},{"key":"ref37","volume-title":"Versal Adaptive SoC Configurable Logic Block Architecture Manual (AM005)","year":"2024"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/3388617"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2010.31"},{"key":"ref40","volume-title":"Yosys open synthesis suite","author":"Wolf","year":"2012"},{"issue":"1","key":"ref41","first-page":"3:1","article-title":"COFFE2: Automatic modelling and optimization of complex and heterogeneous FPGA architectures","volume":"12","author":"Yazdanshenas","year":"2019","journal-title":"ACM Transactions on Reconfigurable Technology and Systems (TRETS)"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/FPL60245.2023.00016"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-14295-6_5"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1155\/2014\/343960"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145708"},{"key":"ref46","volume-title":"Altera Corp","author":"Ganusov","year":"2025"}],"event":{"name":"2025 35th International Conference on Field-Programmable Logic and Applications (FPL)","location":"Leiden, Netherlands","start":{"date-parts":[[2025,9,1]]},"end":{"date-parts":[[2025,9,5]]}},"container-title":["2025 35th International Conference on Field-Programmable Logic and Applications (FPL)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11449056\/11449057\/11449111.pdf?arnumber=11449111","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,27]],"date-time":"2026-03-27T05:27:23Z","timestamp":1774589243000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11449111\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,9,1]]},"references-count":46,"URL":"https:\/\/doi.org\/10.1109\/fpl68686.2025.00016","relation":{},"subject":[],"published":{"date-parts":[[2025,9,1]]}}}