{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,27]],"date-time":"2026-03-27T07:14:10Z","timestamp":1774595650840,"version":"3.50.1"},"reference-count":23,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,9,1]],"date-time":"2025-09-01T00:00:00Z","timestamp":1756684800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,9,1]],"date-time":"2025-09-01T00:00:00Z","timestamp":1756684800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001871","name":"Funda\u00e7\u00e3o para a Ci\u00eancia e a Tecnologia","doi-asserted-by":"publisher","award":["2022.06780.PTDC,UIDB\/50021\/2020,PT\/BD\/154723\/2022"],"award-info":[{"award-number":["2022.06780.PTDC,UIDB\/50021\/2020,PT\/BD\/154723\/2022"]}],"id":[{"id":"10.13039\/501100001871","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,9,1]]},"DOI":"10.1109\/fpl68686.2025.00021","type":"proceedings-article","created":{"date-parts":[[2026,3,26]],"date-time":"2026-03-26T19:48:24Z","timestamp":1774554504000},"page":"68-72","source":"Crossref","is-referenced-by-count":0,"title":["URAM-Based Asynchronous FIFO Design for Improved Throughput and FPGA RAM Usage"],"prefix":"10.1109","author":[{"given":"Martim","family":"Rosado","sequence":"first","affiliation":[{"name":"On behalf of the CMS Collaboration"}]},{"given":"Pedro","family":"Tom\u00e1s","sequence":"additional","affiliation":[{"name":"INESC-ID, Instituto Superior Técnico, Universidade de Lisboa,Portugal"}]},{"given":"Nuno","family":"Roma","sequence":"additional","affiliation":[{"name":"INESC-ID, Instituto Superior Técnico, Universidade de Lisboa,Portugal"}]},{"given":"Andr\u00e9","family":"David","sequence":"additional","affiliation":[{"name":"On behalf of the CMS Collaboration"}]}],"member":"263","reference":[{"key":"ref1","volume-title":"Optimization of on-chip memory on fpga device","author":"Lin","year":"2024"},{"key":"ref2","article-title":"Simulation and synthesis techniques for asynchronous fifo design","volume-title":"SNUG 2002 (Synopsys Users Group Conference, San Jose, CA, 2002) User Papers","volume":"281","author":"Cummings","year":"2002"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.903938"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VLSISOC.2009.6041338"},{"key":"ref5","first-page":"573","article-title":"Advancements in asynchronous fifo design: A review of recent innovations and trends","volume":"10","author":"Chandu","year":"2023","journal-title":"INTERNATIONAL JOURNAL OF RESEARCH AND ANALYTICAL REVIEWS"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.54254\/2755-2721\/2025.19491"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC49171.2020.00014"},{"key":"ref8","article-title":"AMD FPGA FIFO Generator IP","volume-title":"FIFO generator IP user guide"},{"key":"ref9","article-title":"Xilinx Parameterized Macros","volume-title":"XPM user guide from UltraScale Architecture libraries guide"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.23919\/IFIPNetworking55013.2022.9829813"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICC45041.2023.10278875"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM48280.2020.00015"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1002\/nem.2134"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2019.00010"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/WCNC55385.2023.10118631"},{"key":"ref16","volume-title":"High throughput data interfacing","author":"Floros","year":"2021"},{"key":"ref17","volume-title":"Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS923)."},{"key":"ref18","article-title":"AMBA\u00ae AXI\u2122 and ACE\u2122 Protocol Specification","volume-title":"AXI4 protocol specifications from ARM."},{"key":"ref19","article-title":"The Phase-2 Upgrade of the CMS Endcap Calorimeter","volume-title":"CERN","year":"2017"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1088\/1748-0221\/3\/08\/s08004"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1088\/1748-0221\/19\/05\/p05064"},{"issue":"04","key":"ref22","doi-asserted-by":"crossref","first-page":"C04007","DOI":"10.1088\/1748-0221\/17\/04\/C04007","article-title":"Firmware architecture of the back end DAQ system for the CMS high granularity endcap calorimeter detector","volume":"17","author":"Mallios","year":"2022","journal-title":"Journal of Instrumentation"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1088\/1748-0221\/20\/03\/c03028"}],"event":{"name":"2025 35th International Conference on Field-Programmable Logic and Applications (FPL)","location":"Leiden, Netherlands","start":{"date-parts":[[2025,9,1]]},"end":{"date-parts":[[2025,9,5]]}},"container-title":["2025 35th International Conference on Field-Programmable Logic and Applications (FPL)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11449056\/11449057\/11449064.pdf?arnumber=11449064","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,27]],"date-time":"2026-03-27T05:42:24Z","timestamp":1774590144000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11449064\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,9,1]]},"references-count":23,"URL":"https:\/\/doi.org\/10.1109\/fpl68686.2025.00021","relation":{},"subject":[],"published":{"date-parts":[[2025,9,1]]}}}