{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,27]],"date-time":"2026-03-27T07:02:51Z","timestamp":1774594971003,"version":"3.50.1"},"reference-count":15,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,9,1]],"date-time":"2025-09-01T00:00:00Z","timestamp":1756684800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,9,1]],"date-time":"2025-09-01T00:00:00Z","timestamp":1756684800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,9,1]]},"DOI":"10.1109\/fpl68686.2025.00033","type":"proceedings-article","created":{"date-parts":[[2026,3,26]],"date-time":"2026-03-26T19:48:24Z","timestamp":1774554504000},"page":"01-09","source":"Crossref","is-referenced-by-count":0,"title":["Routino: Accelerating FPGA Routing Through Efficient Memory Representation"],"prefix":"10.1109","author":[{"given":"Davide","family":"Nicolini","sequence":"first","affiliation":[{"name":"Politecnico di Torino,Turin,Italy"}]},{"given":"Corrado","family":"De Sio","sequence":"additional","affiliation":[{"name":"Politecnico di Torino,Turin,Italy"}]},{"given":"Eleonora","family":"Vacca","sequence":"additional","affiliation":[{"name":"Politecnico di Torino,Turin,Italy"}]},{"given":"Luca","family":"Sterpone","sequence":"additional","affiliation":[{"name":"Politecnico di Torino,Turin,Italy"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2001.968658"},{"key":"ref2","article-title":"Negotiated A* Routing for FPGAs","volume-title":"Proceedings of the Fifth Canadian Workshop on Field-Programmable Devices","author":"Tessier","year":"1998"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/fpga.1995.242049"},{"key":"ref4","volume-title":"AMD Runtime-First FPGA Interchange Routing Contest","year":"2024"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2018.00030"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-63465-7_226"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/iccd.2017.45"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/tcad.2019.2901243"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/fpl64840.2024.00017"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1462586.1462587"},{"key":"ref11","volume-title":"FPGA interchange schema","year":"2024"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/54.867894"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/FPL50879.2020.00055"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2617593"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/tcad.2023.3272582"}],"event":{"name":"2025 35th International Conference on Field-Programmable Logic and Applications (FPL)","location":"Leiden, Netherlands","start":{"date-parts":[[2025,9,1]]},"end":{"date-parts":[[2025,9,5]]}},"container-title":["2025 35th International Conference on Field-Programmable Logic and Applications (FPL)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11449056\/11449057\/11449112.pdf?arnumber=11449112","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,27]],"date-time":"2026-03-27T05:30:07Z","timestamp":1774589407000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11449112\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,9,1]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/fpl68686.2025.00033","relation":{},"subject":[],"published":{"date-parts":[[2025,9,1]]}}}