{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,27]],"date-time":"2026-03-27T07:14:48Z","timestamp":1774595688313,"version":"3.50.1"},"reference-count":30,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,9,1]],"date-time":"2025-09-01T00:00:00Z","timestamp":1756684800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,9,1]],"date-time":"2025-09-01T00:00:00Z","timestamp":1756684800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,9,1]]},"DOI":"10.1109\/fpl68686.2025.00043","type":"proceedings-article","created":{"date-parts":[[2026,3,26]],"date-time":"2026-03-26T19:48:24Z","timestamp":1774554504000},"page":"254-262","source":"Crossref","is-referenced-by-count":0,"title":["Four-Input Lookup Table (LUT4) and Architectural Enhancements Enable Power Efficient Mid-Range FPGAs"],"prefix":"10.1109","author":[{"given":"Satwant","family":"Singh","sequence":"first","affiliation":[{"name":"Lattice Semiconductor Corp,San Jose,CA,USA"}]},{"given":"Michael","family":"Schneider","sequence":"additional","affiliation":[{"name":"Lattice Semiconductor Corp,San Jose,CA,USA"}]},{"given":"Ziad","family":"Aboud","sequence":"additional","affiliation":[{"name":"Lattice Semiconductor Corp,San Jose,CA,USA"}]},{"given":"Jonathan","family":"Peterson","sequence":"additional","affiliation":[{"name":"Lattice Semiconductor Corp,San Jose,CA,USA"}]},{"given":"Senani","family":"Gunaratna","sequence":"additional","affiliation":[{"name":"Lattice Semiconductor Corp,San Jose,CA,USA"}]},{"given":"Ting","family":"Yew","sequence":"additional","affiliation":[{"name":"Lattice Semiconductor Corp,San Jose,CA,USA"}]},{"given":"Cindy","family":"Lee","sequence":"additional","affiliation":[{"name":"Lattice Semiconductor Corp,San Jose,CA,USA"}]},{"given":"Rick","family":"Crotty","sequence":"additional","affiliation":[{"name":"Lattice Semiconductor Corp,San Jose,CA,USA"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/4.121549"},{"key":"ref2","article-title":"Architecture and Synthesis of Field-Programmable Gate Arrays with Hard-wired Connections","volume-title":"Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada","author":"Chung","year":"1994"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/54.544531"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/280756.280873"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/92.766746"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-48302-1_28"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/92.820764"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.800456"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/611817.611844"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-30117-2_16"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/tvlsi.2004.824300"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1514932.1514956"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2331147.2331152"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2435264.2435292"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/iedm.2014.7046970"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/jproc.2015.2392104"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/2684746.2689077"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.23919\/fpl.2017.8056826"},{"key":"ref19","article-title":"PolarFire FPGA and PolarFire SoC FPGA Fabric User Guide","volume-title":"DS60001725G","year":"2023"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/3174243.3174272"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/3289602.3293906"},{"key":"ref22","article-title":"CrossLink-NX Family Data Sheet","volume-title":"Lattice Semiconductor","year":"2023"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/3373087.3375308"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/3431920.3439300"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS53924.2021.9665516"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/3431920.3439285"},{"key":"ref27","first-page":"4","article-title":"FPGA Architecture: Principles and Progression","volume":"21","author":"Andrew","year":"2022","journal-title":"IEEE Circuits and Systems Magazine"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/3626202.3637572"},{"key":"ref29","article-title":"The Difference Between Small FPGA and Mid-Range FPGA","volume-title":"Lattice Semiconductor Corp","year":"2025"},{"key":"ref30","volume-title":"Solving Challenges in the Mid-Range FPGA Market","author":"Hands","year":"2025"}],"event":{"name":"2025 35th International Conference on Field-Programmable Logic and Applications (FPL)","location":"Leiden, Netherlands","start":{"date-parts":[[2025,9,1]]},"end":{"date-parts":[[2025,9,5]]}},"container-title":["2025 35th International Conference on Field-Programmable Logic and Applications (FPL)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11449056\/11449057\/11449090.pdf?arnumber=11449090","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,27]],"date-time":"2026-03-27T05:43:42Z","timestamp":1774590222000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11449090\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,9,1]]},"references-count":30,"URL":"https:\/\/doi.org\/10.1109\/fpl68686.2025.00043","relation":{},"subject":[],"published":{"date-parts":[[2025,9,1]]}}}