{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,27]],"date-time":"2026-03-27T07:05:27Z","timestamp":1774595127016,"version":"3.50.1"},"reference-count":4,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,9,1]],"date-time":"2025-09-01T00:00:00Z","timestamp":1756684800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,9,1]],"date-time":"2025-09-01T00:00:00Z","timestamp":1756684800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,9,1]]},"DOI":"10.1109\/fpl68686.2025.00064","type":"proceedings-article","created":{"date-parts":[[2026,3,26]],"date-time":"2026-03-26T19:48:24Z","timestamp":1774554504000},"page":"1-1","source":"Crossref","is-referenced-by-count":0,"title":["NPX: Automating Neuromorphic Processor Design from Spike-Based Learning to FPGA Prototyping"],"prefix":"10.1109","author":[{"given":"Kyuseung","family":"Han","sequence":"first","affiliation":[{"name":"Electronics and Telecommunications Research Institute,Daejeon,South Korea"}]},{"given":"Hyeonguk","family":"Jang","sequence":"additional","affiliation":[{"name":"Electronics and Telecommunications Research Institute,Daejeon,South Korea"}]},{"given":"Sukho","family":"Lee","sequence":"additional","affiliation":[{"name":"Electronics and Telecommunications Research Institute,Daejeon,South Korea"}]},{"given":"Sung-Eun","family":"Kim","sequence":"additional","affiliation":[{"name":"Electronics and Telecommunications Research Institute,Daejeon,South Korea"}]},{"given":"Kyudong","family":"Hwang","sequence":"additional","affiliation":[{"name":"Electronics and Telecommunications Research Institute,Daejeon,South Korea"}]},{"given":"Jae-Jin","family":"Lee","sequence":"additional","affiliation":[{"name":"Electronics and Telecommunications Research Institute,Daejeon,South Korea"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2023.3308088"},{"key":"ref2","doi-asserted-by":"crossref","DOI":"10.1109\/FPL68686.2025.00052","article-title":"NeuGEMM: A reorderingfree unified GEMM-Conv2D accelerator for lightweight neuromorphic processors","volume-title":"Proc. of FPL","author":"Jang","year":"2025"},{"key":"ref3","volume-title":"Digilent","year":"2025"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/IJCNN.2011.6033395"}],"event":{"name":"2025 35th International Conference on Field-Programmable Logic and Applications (FPL)","location":"Leiden, Netherlands","start":{"date-parts":[[2025,9,1]]},"end":{"date-parts":[[2025,9,5]]}},"container-title":["2025 35th International Conference on Field-Programmable Logic and Applications (FPL)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11449056\/11449057\/11449133.pdf?arnumber=11449133","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,27]],"date-time":"2026-03-27T05:32:17Z","timestamp":1774589537000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11449133\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,9,1]]},"references-count":4,"URL":"https:\/\/doi.org\/10.1109\/fpl68686.2025.00064","relation":{},"subject":[],"published":{"date-parts":[[2025,9,1]]}}}