{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T21:01:50Z","timestamp":1725483710085},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/fpt.2002.1188675","type":"proceedings-article","created":{"date-parts":[[2003,10,1]],"date-time":"2003-10-01T10:56:02Z","timestamp":1065005762000},"page":"142-147","source":"Crossref","is-referenced-by-count":6,"title":["Implementing logic in FPGA memory arrays: heterogeneous memory architectures"],"prefix":"10.1109","author":[{"given":"S.J.E.","family":"Wilton","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/275107.275137"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"97","DOI":"10.1109\/FPGA.1995.242047","article-title":"architecture of centralized field-configurable memory","author":"wilton","year":"1995","journal-title":"Third International ACM Symposium on Field-Programmable Gate Arrays"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1996.510530"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/258305.258307"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1998.694978"},{"key":"ref15","article-title":"SIS: A system for sequential circuit analysis","author":"sentovich","year":"1992","journal-title":"Technical Report UCB\/ERL M92\/41 Electronics Research Lab"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/43.273754"},{"journal-title":"Architectures and algorithms for field-programmable gate arrays with embedded memory","year":"1997","author":"wilton","key":"ref17"},{"journal-title":"Programmable Logic Device Family Datasheet","year":"2002","key":"ref4"},{"journal-title":"APEX 20K Programmable Logic Device Family Data Sheet ver 2 0","year":"2002","key":"ref3"},{"journal-title":"Datasheet 3200DX Field-programmable Gate Arrays","year":"1995","key":"ref6"},{"journal-title":"XC4000E and XC4000X Series Field Programmable Gate Arrays ver 1 6","year":"1999","key":"ref5"},{"journal-title":"Datasheet IspLSI and PLSI 6192 High Density Programmable Logic with Dedicated Memory and Register\/Counter Modules","year":"1996","key":"ref8"},{"journal-title":"Actel's Reprogrammable SPGAs 1996","year":"0","key":"ref7"},{"journal-title":"FLEX 10K Embedded Programmable Logic Family Data Sheet ver 4 01","year":"2001","key":"ref2"},{"journal-title":"Virtex 2 5 V Field Programmable Gate Arrays ver 1 6","article-title":"Xilinx, Inc","year":"1999","key":"ref1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1995.518232"}],"event":{"name":"2002 IEEE International Conference on Field-Programmable Technology (FPT)","acronym":"FPT-02","location":"Hong Kong, China"},"container-title":["2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8456\/26638\/01188675.pdf?arnumber=1188675","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,15]],"date-time":"2017-06-15T20:57:08Z","timestamp":1497560228000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1188675\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/fpt.2002.1188675","relation":{},"subject":[]}}