{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T10:15:23Z","timestamp":1742379323061},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/fpt.2002.1188685","type":"proceedings-article","created":{"date-parts":[[2003,10,1]],"date-time":"2003-10-01T14:56:02Z","timestamp":1065020162000},"page":"219-226","source":"Crossref","is-referenced-by-count":8,"title":["Synthesizing datapath circuits for FPGAs with emphasis on area minimization"],"prefix":"10.1109","author":[{"given":"A.","family":"Ye","sequence":"first","affiliation":[]},{"given":"J.","family":"Rose","sequence":"additional","affiliation":[]},{"given":"D.","family":"Lewis","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2000.896511"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2000.878327"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296444"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1996.564808"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.1994.282636"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/43.709401"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.2000.903401"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/2.612254"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1155\/1996\/95942"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-5145-4"},{"key":"ref6","first-page":"877","article-title":"Performance Optimization Using Template Mapping for Datapath-Intensive High-Level Synthesis","author":"miguel","year":"1996","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"ref5","first-page":"123","article-title":"Fast Module Mapping and Placement for Datapaths in FPGAs","author":"timothy","year":"1998","journal-title":"Proceedings of the 1998 ACM\/SIGDA Sixth International Symposium on Field Programmable Gate Arrays"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/228370.228392"},{"key":"ref7","first-page":"87","article-title":"The Chimaera Reconfigurable Functional Unit","author":"scott","year":"1997","journal-title":"IEEE Symp FPGA s for Custom Computing Machines"},{"journal-title":"Synopsys Design Compiler Application Manual","year":"1999","key":"ref2"},{"journal-title":"Pico-Java Processor Design Documentation","year":"1999","key":"ref1"},{"key":"ref9","first-page":"471","article-title":"Module Compaction in FPGA-based Regular Datapaths","author":"koch","year":"1996","journal-title":"Proceedings of the 33rd Design Automation Conference"}],"event":{"name":"2002 IEEE International Conference on Field-Programmable Technology (FPT)","acronym":"FPT-02","location":"Hong Kong, China"},"container-title":["2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8456\/26638\/01188685.pdf?arnumber=1188685","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T22:51:29Z","timestamp":1489445489000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1188685\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/fpt.2002.1188685","relation":{},"subject":[]}}