{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,23]],"date-time":"2025-04-23T04:49:29Z","timestamp":1745383769967,"version":"3.28.0"},"reference-count":55,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/fpt.2002.1188690","type":"proceedings-article","created":{"date-parts":[[2003,10,1]],"date-time":"2003-10-01T14:56:02Z","timestamp":1065020162000},"page":"260-267","source":"Crossref","is-referenced-by-count":13,"title":["A fine-grained reconfigurable logic array based on double gate transistors"],"prefix":"10.1109","author":[{"given":"P.","family":"Beckett","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1016\/0038-1101(95)00040-Z"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1016\/S0167-9317(98)00106-3"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2001.979527"},{"key":"ref32","doi-asserted-by":"crossref","DOI":"10.1023\/A:1020704919992","article-title":"A 3-D Atomistic Study of Archetypal Double Gate MOSFET Structures","author":"brown","year":"2002","journal-title":"Journal of Computational Electronics vol (in press)"},{"key":"ref31","doi-asserted-by":"crossref","DOI":"10.1109\/FPGA.1996.242346","article-title":"Entropy, Counting, and Programmable Interconnect","author":"dehon","year":"1996","journal-title":"presented at ACM\/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA'96)"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/378239.378459"},{"key":"ref37","article-title":"Gate Length Scaling and Threshold Voltage Control of Double-Gate MOSFETs","author":"chang","year":"0","journal-title":"presented at the Electron Devices Meeting"},{"key":"ref36","article-title":"Experimental Evaluation of Carrier Transport and Device Design for Planar Symmetric\/Asymmetric Double-Gate\/Ground-Plane CMOSFETs","author":"leong","year":"0","journal-title":"presented at Electron Devices Meeting 2001 IEDM Technical Digest International Washingto DC"},{"article-title":"Idealized SOI-Si Double Gate NMOSFET Device, Rev. 12-8”–00","year":"0","author":"ren","key":"ref35"},{"journal-title":"nanoHub The Nanotechnology Simulation Hub","year":"0","key":"ref34"},{"key":"ref28","article-title":"The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density","author":"ahmed","year":"2000","journal-title":"presented at FPGA 2000"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/4.121549"},{"key":"ref29","article-title":"The Microprocessor is No Longer General Purpose: Why Future Reconfigurable Platforms Will Win","author":"hartenstein","year":"1996","journal-title":"presented at Second Annual IEEE International Conference on Innovative Systems in Silicon IEEE"},{"key":"ref2","article-title":"Silicon Nanoelectronics: 100nm Barriers and Potential Solutions","author":"parihar","year":"1998","journal-title":"Paper Presented at IEEE\/SEMI Advanced Semiconductor Manufacturing Conference"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/5.663540"},{"key":"ref20","article-title":"Reconfigurable Architectures for General-Purpose Computing","author":"dehon","year":"1996","journal-title":"MIT Massachusetts A I Technical Report 1586"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/360276.360323"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/5.920579"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/40.782564"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/360276.360331"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/2.803637"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/5.920580"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1049\/el:20010961"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1145\/228370.228372"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1143\/JJAP.35.1366"},{"key":"ref54","article-title":"Interconnect Technology for Giga-Scale Integration","author":"liu","year":"1998","journal-title":"presented at Intl Conf on Solid State and Integrated Circuit Technology"},{"key":"ref53","doi-asserted-by":"crossref","first-page":"37","DOI":"10.1109\/101.666590","article-title":"Clock-cycle Estimation and Test Challenges for Future Microprocessors","author":"fisher","year":"1998","journal-title":"IEEE Circuits and Devices"},{"article-title":"Programming Architectures for Run-Time Reconfigurable Systems","year":"2000","author":"compton","key":"ref52"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2001.937446"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1126\/science.289.5476.94"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1016\/S0038-1101(02)00031-X"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"1317","DOI":"10.1126\/science.1065824","article-title":"Logic Circuits with Carbon Nanotube Transistors","volume":"294","author":"bachtold","year":"2001","journal-title":"Science"},{"key":"ref13","article-title":"Array-Based Architecture for Molecular Electronics","author":"dehon","year":"0","journal-title":"presented at First Workshop on Non-Silicon Computation (NSC-1)"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1088\/0957-4484\/4\/1\/004"},{"key":"ref15","article-title":"A Potentially Implementable FPGA for Quantum Dot Cellular Automata","author":"niemier","year":"0","journal-title":"presented at First Workshop on Non-Silicon Computation (NSC-1)"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1016\/S0038-1101(01)00330-6"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/55.936358"},{"article-title":"Logical Elements Based on Dual Mos Transistors","year":"0","author":"rakitin","key":"ref18"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296422"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/5.705525"},{"key":"ref3","article-title":"3rd Annual Report, Autonomous Nanoelectronic Systems With Extended Replication and Signalling, ANSWERS","author":"forshaw","year":"2000","journal-title":"University College London Image Processing Group London U K Technical Report"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/275107.275113"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/54.655177"},{"key":"ref8","article-title":"Technology Roadmap for Nanoelectronics","author":"compano","year":"2000","journal-title":"2nd ed European Commission IST Programme - Future and Emerging Technologies"},{"article-title":"The Price of Routing in FPGAs","year":"0","author":"de dinechin","key":"ref7"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1116\/1.1339011"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/5.915377"},{"key":"ref46","doi-asserted-by":"crossref","first-page":"174","DOI":"10.1088\/0957-4484\/10\/2\/312","article-title":"Tunnelling-Based SRAM","volume":"10","author":"van","year":"1999","journal-title":"Nanotechnology"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/4.127345"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/55.192801"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/5.752517"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1143\/JJAP.35.2090"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/ESSDERC.2001.195252"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1063\/1.1480877"},{"key":"ref43","doi-asserted-by":"crossref","first-page":"453","DOI":"10.1021\/nl015606f","article-title":"Carbon Nanotube Inter-and Intramolecular Logic Gates","volume":"1","author":"derycke","year":"2001","journal-title":"Nano Letters"}],"event":{"name":"2002 IEEE International Conference on Field-Programmable Technology (FPT)","acronym":"FPT-02","location":"Hong Kong, China"},"container-title":["2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8456\/26638\/01188690.pdf?arnumber=1188690","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T00:57:09Z","timestamp":1497574629000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1188690\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":55,"URL":"https:\/\/doi.org\/10.1109\/fpt.2002.1188690","relation":{},"subject":[]}}