{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,8,18]],"date-time":"2026-08-18T00:15:07Z","timestamp":1787012107734,"version":"build-2736575974"},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/fpt.2002.1188704","type":"proceedings-article","created":{"date-parts":[[2003,10,1]],"date-time":"2003-10-01T10:56:02Z","timestamp":1065005762000},"page":"332-335","source":"Crossref","is-referenced-by-count":8,"title":["Testing for resistive open defects in FPGAs"],"prefix":"10.1109","author":[{"given":"M.B.","family":"Tahoori","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2001.966731"},{"key":"ref11","first-page":"25","article-title":"High Volume Microprocessor Test Escapes, An Analysis of Defects Our Tests Are Missing","author":"wayne","year":"1998","journal-title":"Proc Int'l Test Conf"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1995.529875"},{"key":"ref13","article-title":"Automatic Configuration Generation for Interconnect Testing in Switch-Based FPGAs","author":"tahoori","year":"2002","journal-title":"CRC TR 02&#x2013;2"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.2000.843843"},{"key":"ref15","year":"2002","journal-title":"The programmable Logic Data Book 2002 Xilinx Inc"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1999.766661"},{"key":"ref3","first-page":"215","article-title":"Improving Diagnostic Resolution of Delay Faults in FPGAs by Exploiting Reconfigurability","author":"dastidar","year":"2001","journal-title":"Proc IEEE Int Symp Defect Fault Tolerance"},{"key":"ref6","first-page":"758","article-title":"A New Path Oriented Effect-Cause Methodology to Diagnose Delay Failures","author":"hsu","year":"1998","journal-title":"Proc Int'l Test Conf"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1994.527983"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/OLT.2000.856610"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2001.952312"},{"key":"ref2","article-title":"FPGA interconnect structure with high-speed high fanout capability","author":"bauer","year":"1999"},{"key":"ref1","first-page":"467","article-title":"Defect-Based delay testing of Resistive Vias-Contacts","author":"baker","year":"1999","journal-title":"Proc of International Test Conference"},{"key":"ref9","article-title":"Numerical Data and Functional Relationship in Science and Technology. New Series","volume":"15","author":"bornstein","year":"1996","journal-title":"sub vol A"}],"event":{"name":"2002 IEEE International Conference on Field-Programmable Technology (FPT)","location":"Hong Kong, China","acronym":"FPT-02"},"container-title":["2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8456\/26638\/01188704.pdf?arnumber=1188704","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T18:12:36Z","timestamp":1489428756000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1188704\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/fpt.2002.1188704","relation":{},"subject":[]}}