{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,26]],"date-time":"2025-10-26T13:57:23Z","timestamp":1761487043334},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/fpt.2002.1188733","type":"proceedings-article","created":{"date-parts":[[2003,10,1]],"date-time":"2003-10-01T14:56:02Z","timestamp":1065020162000},"page":"449-452","source":"Crossref","is-referenced-by-count":15,"title":["Alternatives in FPGA-based SAD implementations"],"prefix":"10.1109","author":[{"given":"S.","family":"Wong","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"B.","family":"Stougie","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.","family":"Cotofana","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2002.1106759"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/505306.505328"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1996.564773"},{"key":"ref6","first-page":"545","article-title":"Run-time Adaptive Flexible Instruction Processors","author":"seng","year":"2002","journal-title":"Proceedings of the Conference on Field Programmable Logic 2002 (FPL2002)"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/CMPCON.1996.501790"},{"key":"ref8","article-title":"The Sum-Absolute-Difference Motion Estimation Accelerator","author":"vassiliadis","year":"2000","journal-title":"Proceedings of the 24th Euromicro Conference"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2001.955061"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ARVLSI.1999.756035"},{"key":"ref9","first-page":"275","article-title":"The MOLEN ?&#x00B5;&#x2013;coded Processor","author":"vassiliadis","year":"2001","journal-title":"Proceedings of the Conference on Field Programmable Logic 2001 (FPL2001)"},{"journal-title":"Virtex-II 1 5V FPGA Family Detailed Functional Description","year":"0","key":"ref1"}],"event":{"name":"2002 IEEE International Conference on Field-Programmable Technology (FPT)","acronym":"FPT-02","location":"Hong Kong, China"},"container-title":["2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8456\/26638\/01188733.pdf?arnumber=1188733","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T17:22:02Z","timestamp":1489425722000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1188733\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/fpt.2002.1188733","relation":{},"subject":[]}}