{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,13]],"date-time":"2026-06-13T16:26:57Z","timestamp":1781368017558,"version":"3.54.1"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,12]]},"DOI":"10.1109\/fpt.2010.5681654","type":"proceedings-article","created":{"date-parts":[[2011,1,7]],"date-time":"2011-01-07T14:09:43Z","timestamp":1294409383000},"page":"45-52","source":"Crossref","is-referenced-by-count":4,"title":["Multiple data set reduction on FPGAs"],"prefix":"10.1109","author":[{"given":"Yi-Gang","family":"Tai","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Chia-Tien Dan","family":"Lo","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Kleanthis","family":"Psarris","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","year":"0","journal-title":"Xilinx Inc"},{"key":"ref11","year":"0","journal-title":"Mentor Graphics Corporation"},{"key":"ref12","year":"2006","journal-title":"Xilinx Floating-Point Operator v3 0 Xilinx Inc"},{"key":"ref13","article-title":"Parallel tiled QR factorization for multicore architectures","author":"buttari","year":"2007","journal-title":"LAPack Working Notes"},{"key":"ref14","article-title":"Enhancing Parallelism of Tile QR Factorization for Multicore Architectures","author":"hadri","year":"2009","journal-title":"LAPack Working Notes"},{"key":"ref4","year":"0","journal-title":"Undisclosed Paper"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/12.73591"},{"key":"ref6","doi-asserted-by":"crossref","DOI":"10.1109\/CAHPC.2005.28","article-title":"High-performance and area-efficient reduction circuits on fpgas","author":"zhuo","year":"2005","journal-title":"Proceedings of the 17th International Symposium on Computer Architecture and High Performance Computing"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2005.165"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2006.8"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2005.42"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1985.1676580"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2007.1068"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2006.11"}],"event":{"name":"2010 International Conference on Field-Programmable Technology (FPT)","location":"Beijing, China","start":{"date-parts":[[2010,12,8]]},"end":{"date-parts":[[2010,12,10]]}},"container-title":["2010 International Conference on Field-Programmable Technology"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5677390\/5681421\/05681654.pdf?arnumber=5681654","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,7]],"date-time":"2019-06-07T17:38:10Z","timestamp":1559929090000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5681654\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,12]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/fpt.2010.5681654","relation":{},"subject":[],"published":{"date-parts":[[2010,12]]}}}