{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T07:05:24Z","timestamp":1725779124817},"reference-count":22,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,12]]},"DOI":"10.1109\/fpt.2012.6412128","type":"proceedings-article","created":{"date-parts":[[2013,1,25]],"date-time":"2013-01-25T19:47:11Z","timestamp":1359143231000},"page":"151-158","source":"Crossref","is-referenced-by-count":23,"title":["iDEA: A DSP block based FPGA soft processor"],"prefix":"10.1109","author":[{"given":"Hui Yan","family":"Cheah","sequence":"first","affiliation":[]},{"given":"Suhaib A.","family":"Fahmy","sequence":"additional","affiliation":[]},{"given":"Douglas L.","family":"Maskell","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2009.5470118"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2012.6339163"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950420"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2012.55"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1145\/1450095.1450107"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2005.1515690"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2011.51"},{"key":"14","first-page":"222","article-title":"Vector processing as a softcore CPU accelerator","author":"yu","year":"0","journal-title":"Proceedings of ACM\/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA) Feb 2008"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2007.4295266"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2011.14"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145734"},{"journal-title":"Nios II Processor Design","year":"2011","key":"3"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2010.5681463"},{"journal-title":"UG081 MicroBlaze Processor Reference Guide","year":"2011","key":"2"},{"journal-title":"UG369 Virtex-6 FPGA DSP48E1 Slice User Guide","year":"2011","key":"1"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145731"},{"key":"7","article-title":"Experiences with softcore processor design","author":"plavec","year":"0","journal-title":"Proceedings of International Parallel and Distributed Processing Symposium (IPDPS) Apr 2005"},{"journal-title":"GRLIB IP Library User's Manual","year":"2012","key":"6"},{"journal-title":"LatticeMico32 Processor Reference Manual","year":"2009","key":"5"},{"journal-title":"Cortex-M1 Processor","year":"2011","key":"4"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2011.154"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5456903"}],"event":{"name":"2012 International Conference on Field-Programmable Technology (FPT)","start":{"date-parts":[[2012,12,10]]},"location":"Seoul, Korea (South)","end":{"date-parts":[[2012,12,12]]}},"container-title":["2012 International Conference on Field-Programmable Technology"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6395855\/6412099\/06412128.pdf?arnumber=6412128","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,22]],"date-time":"2017-03-22T20:22:36Z","timestamp":1490214156000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6412128\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,12]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/fpt.2012.6412128","relation":{},"subject":[],"published":{"date-parts":[[2012,12]]}}}