{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T22:47:40Z","timestamp":1725662860913},"reference-count":7,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,12]]},"DOI":"10.1109\/fpt.2014.7082805","type":"proceedings-article","created":{"date-parts":[[2015,4,13]],"date-time":"2015-04-13T21:56:12Z","timestamp":1428962172000},"page":"306-309","source":"Crossref","is-referenced-by-count":2,"title":["A novel three-dimensional FPGA architecture with high-speed serial communication links"],"prefix":"10.1109","author":[{"given":"Takuya","family":"Kajiwara","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Qian","family":"Zhao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Motoki","family":"Amagasaki","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Masahiro","family":"Iida","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Morituro","family":"Kuga","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Toshinori","family":"Sueyoshi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2010.31"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2009.4796515"},{"article-title":"The Verilog-to-Routing (VTR) Project for FPGAs","year":"0","author":"jason","key":"ref6"},{"year":"0","key":"ref5","article-title":"ABC: A System for Sequential Synthesis and Verification"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1587\/transinf.E96.D.1602"},{"key":"ref2","first-page":"291","article-title":"An Easily Testable Routing Architecture And Effecient Test Technique","author":"inoue","year":"2011","journal-title":"Proc of FPL"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2013.6673274"}],"event":{"name":"2014 International Conference on Field-Programmable Technology (FPT)","start":{"date-parts":[[2014,12,10]]},"location":"Shanghai, China","end":{"date-parts":[[2014,12,12]]}},"container-title":["2014 International Conference on Field-Programmable Technology (FPT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7063887\/7082738\/07082805.pdf?arnumber=7082805","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T19:43:02Z","timestamp":1490384582000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7082805\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,12]]},"references-count":7,"URL":"https:\/\/doi.org\/10.1109\/fpt.2014.7082805","relation":{},"subject":[],"published":{"date-parts":[[2014,12]]}}}