{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T16:40:44Z","timestamp":1742402444135},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/ftdcs.2003.1204336","type":"proceedings-article","created":{"date-parts":[[2004,6,22]],"date-time":"2004-06-22T20:27:43Z","timestamp":1087936063000},"page":"219-224","source":"Crossref","is-referenced-by-count":5,"title":["Queue management for QoS provision build on network processor"],"prefix":"10.1109","author":[{"family":"Wenjiang Zhou","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Chuang Lin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Yin Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Zhangxi Tan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/90.502236"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/90.251892"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/49.772449"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/INFCOM.2001.916645"},{"journal-title":"IBM Corporation IBM PowerNP NP4GS3 Network Processor Solutions Product Overview","year":"2001","key":"ref14"},{"journal-title":"Vitesse Semiconductor Corporation IQ2000 Network Processor Product Brief","year":"2000","key":"ref15"},{"key":"ref4","article-title":"Design space exploration of network processor architectures","author":"thiele","year":"0","journal-title":"Network Processor Design 2002 Design Principles and Practices"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/335231.335237"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/502034.502056"},{"key":"ref5","article-title":"Design tradeoffs for embedded network processors","author":"wolf","year":"2000","journal-title":"Technical Report WUCS-00-24 Department of Computer Science Washington University in St Louis"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/49.772432"},{"key":"ref7","article-title":"Evaluating network processors in IP forwarding","author":"spalink","year":"2000","journal-title":"Princeton University Technical Report TR-626-00"},{"journal-title":"Intel Corporation Programming using IXP1200","year":"0","key":"ref2"},{"journal-title":"Intel Corporation IXP1200 Hardware Reference Manual","year":"2000","key":"ref1"},{"key":"ref9","first-page":"1164","article-title":"Comparison of buffer allocation schemes in ATM switched: complete sharing, partial sharing and dedicated allocation","author":"causey","year":"1994","journal-title":"ICC"}],"event":{"name":"The Ninth IEEE Workshop on Future Trends of Distributed Computing Systems, 2003. FTDCS 2003.","location":"San Juan, Puerto Rico"},"container-title":["The Ninth IEEE Workshop on Future Trends of Distributed Computing Systems, 2003. FTDCS 2003. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8565\/27118\/01204336.pdf?arnumber=1204336","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T21:24:14Z","timestamp":1489440254000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1204336\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/ftdcs.2003.1204336","relation":{},"subject":[]}}