{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,21]],"date-time":"2025-08-21T18:02:09Z","timestamp":1755799329970,"version":"3.44.0"},"reference-count":22,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,11,1]],"date-time":"2019-11-01T00:00:00Z","timestamp":1572566400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,11,1]],"date-time":"2019-11-01T00:00:00Z","timestamp":1572566400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,11]]},"DOI":"10.1109\/globalsip45357.2019.8969292","type":"proceedings-article","created":{"date-parts":[[2020,1,31]],"date-time":"2020-01-31T00:51:57Z","timestamp":1580431917000},"page":"1-5","source":"Crossref","is-referenced-by-count":2,"title":["A Block-Floating-Point Arithmetic Based FPGA Accelerator for Convolutional Neural Networks"],"prefix":"10.1109","author":[{"given":"Heshan","family":"Zhang","sequence":"first","affiliation":[{"name":"Northwestern Polytechnical University,School of Electronics and Information,Xi’an,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhenyu","family":"Liu","sequence":"additional","affiliation":[{"name":"Tsinghua University,RIIT&TNList,Beijing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Guanwen","family":"Zhang","sequence":"additional","affiliation":[{"name":"Northwestern Polytechnical University,School of Electronics and Information,Xi’an,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jiwu","family":"Dai","sequence":"additional","affiliation":[{"name":"Northwestern Polytechnical University,School of Electronics and Information,Xi’an,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiaocong","family":"Lian","sequence":"additional","affiliation":[{"name":"Tsinghua University,Department of Automation,Beijing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wei","family":"Zhou","sequence":"additional","affiliation":[{"name":"Northwestern Polytechnical University,School of Electronics and Information,Xi’an,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiangyang","family":"Ji","sequence":"additional","affiliation":[{"name":"Tsinghua University,Department of Automation,Beijing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.5555\/2999134.2999257"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.4324\/9781410605337-29"},{"article-title":"Very deep convolutional networks for large-scale image recognition","year":"2014","author":"Simonyan","key":"ref3"},{"key":"ref4","article-title":"NVIDIA cuDNN GPU accelerated deep learning"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2684746.2689060"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2847265"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2705069"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2016.7577308"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783720"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2616357"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/GlobalSIP.2017.8309067"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2913958"},{"author":"Migacz","key":"ref13","article-title":"8-bit inference with TensorRT"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1609\/aaai.v32i1.11334"},{"article-title":"Deep compression: Compressing deep neural networks with pruning trained quantization and huffman coding","year":"2015","author":"Han","key":"ref15"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757323"},{"key":"ref17","article-title":"CUDA Toolkit Documentation: Floating Point and IEEE 754"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2647868.2654889"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"ref20","article-title":"Imagenet"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062244"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240801"}],"event":{"name":"2019 IEEE Global Conference on Signal and Information Processing (GlobalSIP)","start":{"date-parts":[[2019,11,11]]},"location":"Ottawa, ON, Canada","end":{"date-parts":[[2019,11,14]]}},"container-title":["2019 IEEE Global Conference on Signal and Information Processing (GlobalSIP)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8961038\/8969075\/08969292.pdf?arnumber=8969292","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,19]],"date-time":"2025-08-19T18:10:46Z","timestamp":1755627046000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8969292\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,11]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/globalsip45357.2019.8969292","relation":{},"subject":[],"published":{"date-parts":[[2019,11]]}}}