{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T15:54:48Z","timestamp":1725465288024},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/glocom.2003.1259010","type":"proceedings-article","created":{"date-parts":[[2004,3,22]],"date-time":"2004-03-22T09:34:28Z","timestamp":1079948068000},"page":"4158-4162","source":"Crossref","is-referenced-by-count":3,"title":["A conflict-free memory banking architecture for fast VOQ packet buffers"],"prefix":"10.1109","author":[{"given":"J.","family":"Garcia","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"L.","family":"Cerda","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.","family":"Corbal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Valero","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"crossref","DOI":"10.1109\/CONECT.2002.1039251","article-title":"A fourterabit single-stage packet switch withlarge round-trip time support","author":"abel","year":"2002","journal-title":"10th Symposium on High Performance Interconnects"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/35.888260"},{"journal-title":"Hitachi HM5257XXb series 2000","article-title":"Hitachi 166 mhz sdram","year":"0","key":"ref10"},{"journal-title":"Gigabit Network Workshop GBN 2001","article-title":"Techniques for fast packet buffers","year":"2001","key":"ref6"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/40.641593"},{"key":"ref5","article-title":"Analysis of a memory architecture for fast packet buffers","author":"lyer","year":"2001","journal-title":"Proc IEEE Workshop High Performance Switching and Routing"},{"key":"ref8","first-page":"324","article-title":"Performance evaluation of vector accesses in parallel memories using a skewed storage scheme","year":"1986","journal-title":"International Symposium on Computer Architecture ISCA"},{"year":"2002","key":"ref7","article-title":"Designing Packet Buffers for Router Line Cards (Draft version)"},{"key":"ref2","article-title":"Fast switched backplane for a gigabit switched router","author":"mckeown","year":"0","journal-title":"Cisco Systems White Paper"},{"key":"ref9","article-title":"A conflict-free memory banking architecture for fast packet buffers","author":"garc\u00eda","year":"2002","journal-title":"Tech Rep UPC-DAC-2002-50"},{"key":"ref1","first-page":"343","article-title":"High-performance multi-queue buffers for vlsi communication switches","author":"and","year":"1988","journal-title":"15th Annual International Symposium on Computer Architecture"}],"event":{"name":"GLOBECOM '03. IEEE Global Telecommunications Conference","acronym":"GLOCOM-03","location":"San Francisco, CA, USA"},"container-title":["GLOBECOM '03. IEEE Global Telecommunications Conference (IEEE Cat. No.03CH37489)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8900\/28138\/01259010.pdf?arnumber=1259010","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T00:26:54Z","timestamp":1497572814000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1259010\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/glocom.2003.1259010","relation":{},"subject":[]}}