{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,18]],"date-time":"2026-01-18T10:20:27Z","timestamp":1768731627462,"version":"3.49.0"},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/glocom.2004.1378472","type":"proceedings-article","created":{"date-parts":[[2005,4,5]],"date-time":"2005-04-05T13:41:25Z","timestamp":1112708485000},"page":"2583-2588","source":"Crossref","is-referenced-by-count":8,"title":["High-performance decoders for regular and irregular repeat-accumulate codes"],"prefix":"10.1109","volume":"4","author":[{"given":"M.M.","family":"Mansour","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","article-title":"On quasi-cyclic repeat-accumulate codes","author":"tanner","year":"1999","journal-title":"Proc 37th Annu Allerton Conf"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2003.1205886"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/BF02126799"},{"key":"ref13","first-page":"248","article-title":"Constructions of LDPC codes using Ramanujan graphs and ideas from Margulis","author":"rosenthal","year":"2000","journal-title":"Proc of the 38th Allerton Conf"},{"key":"ref14","article-title":"Construction of LDPC codes from Ramanujan graphs","author":"mansour","year":"2002","journal-title":"Conf on Info Science and Systems"},{"key":"ref15","first-page":"215","article-title":"On the architecture-aware structure of LDPC codes from generalized Ramanujan graphs and their decoder architectures","author":"mansour","year":"2003","journal-title":"Conf on Info Science and Systems"},{"key":"ref16","first-page":"284","article-title":"Low-power VLSI decoder architectures for LDPC codes","author":"mansour","year":"2002","journal-title":"ISLPED 2002"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/GLOCOM.2002.1188425"},{"key":"ref18","first-page":"137","article-title":"A 1.6-Gbit\/sec 2048-bit programmable and code-rate tunable LDPC decoder chip","author":"mansour","year":"2003","journal-title":"3rd Int Symp Turbo Codes"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/18.910578"},{"key":"ref3","doi-asserted-by":"crossref","DOI":"10.7551\/mitpress\/4347.001.0001","author":"gallager","year":"1963","journal-title":"Low-Density Parity-Check Codes"},{"key":"ref6","first-page":"201","article-title":"Coding theorems for turbo-like codes","author":"divsalar","year":"1998","journal-title":"Proc of the 36th Allerton Conf"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.817545"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.1981.1056404"},{"key":"ref7","first-page":"1","article-title":"Irregular repeat-accumulate codes","author":"jin","year":"2000","journal-title":"Proc 2nd Int Conf Turbo Codes"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.1974.1055186"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ICC.1993.397441"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.2004.831778"}],"event":{"name":"IEEE Global Telecommunications Conference, 2004. GLOBECOM '04.","location":"Dallas, TX, USA","acronym":"GLOCOM-04"},"container-title":["IEEE Global Telecommunications Conference, 2004. GLOBECOM '04."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9481\/30080\/01378472.pdf?arnumber=1378472","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,4,6]],"date-time":"2020-04-06T17:54:57Z","timestamp":1586195697000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1378472\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/glocom.2004.1378472","relation":{},"subject":[]}}