{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,3]],"date-time":"2026-10-03T15:30:08Z","timestamp":1791041408201,"version":"4.1.0"},"reference-count":7,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,8,21]],"date-time":"2022-08-21T00:00:00Z","timestamp":1661040000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,8,21]],"date-time":"2022-08-21T00:00:00Z","timestamp":1661040000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,8,21]]},"DOI":"10.1109\/hcs55958.2022.9895600","type":"proceedings-article","created":{"date-parts":[[2022,9,26]],"date-time":"2022-09-26T16:59:33Z","timestamp":1664211573000},"page":"1-14","source":"Crossref","is-referenced-by-count":6,"title":["A 13.7\u03bcJ\/prediction 88% Accuracy CIFAR-10 Single-Chip Wired-logic Processor in 16-nm FPGA using Non-Linear Neural Network"],"prefix":"10.1109","author":[{"given":"Yao-Chung","family":"Hsu","sequence":"first","affiliation":[{"name":"The University of Tokyo"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Atsutake","family":"Kosuge","sequence":"additional","affiliation":[{"name":"The University of Tokyo"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Rei","family":"Sumikawa","sequence":"additional","affiliation":[{"name":"The University of Tokyo"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Kota","family":"Shiba","sequence":"additional","affiliation":[{"name":"The University of Tokyo"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mototsugu","family":"Hamada","sequence":"additional","affiliation":[{"name":"The University of Tokyo"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Tadahiro","family":"Kuroda","sequence":"additional","affiliation":[{"name":"The University of Tokyo"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1073\/pnas.1604850113"},{"key":"ref3","first-page":"65","author":"umuroglu","year":"2017","journal-title":"INT&#x2019;L SYMP ON FPGA"},{"key":"ref6","first-page":"1","author":"moons","year":"2018","journal-title":"CICC"},{"key":"ref5","first-page":"222","author":"bankman","year":"2018","journal-title":"ISSCC"},{"key":"ref7","first-page":"4","volume":"3","author":"kosuge","year":"2022","journal-title":"IEEE OJCAS"},{"key":"ref2","first-page":"15","author":"zhao","year":"2017","journal-title":"INT&#x2019;L SYMP ON FPGA"},{"key":"ref1","first-page":"1","author":"lai","year":"2018"}],"event":{"name":"2022 IEEE Hot Chips 34 Symposium (HCS)","location":"Cupertino, CA, USA","start":{"date-parts":[[2022,8,21]]},"end":{"date-parts":[[2022,8,23]]}},"container-title":["2022 IEEE Hot Chips 34 Symposium (HCS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9895464\/9895476\/09895600.pdf?arnumber=9895600","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,10,14]],"date-time":"2022-10-14T16:49:07Z","timestamp":1665766147000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9895600\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,8,21]]},"references-count":7,"URL":"https:\/\/doi.org\/10.1109\/hcs55958.2022.9895600","relation":{},"subject":[],"published":{"date-parts":[[2022,8,21]]}}}