{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T15:52:29Z","timestamp":1780674749373,"version":"3.54.1"},"reference-count":14,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/hldvt.2002.1224432","type":"proceedings-article","created":{"date-parts":[[2003,10,1]],"date-time":"2003-10-01T10:56:02Z","timestamp":1065005762000},"page":"77-82","source":"Crossref","is-referenced-by-count":22,"title":["Generating concurrent test-programs with collisions for multi-processor verification"],"prefix":"10.1109","author":[{"given":"A.","family":"Adir","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"G.","family":"Shurek","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/PCCC.1995.472514"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/PCCC.1995.472462"},{"key":"ref12","first-page":"34","article-title":"A simulation-based approach to architectural verification of multiprocessor systems","author":"saba","year":"1995","journal-title":"IEEE 14'th Annual IPCCC"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/PCCC.1995.472463"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1137\/1.9780898719789"},{"key":"ref4","article-title":"X-gen: A generic random stimuli. generator for systems and SoCs","author":"emek","year":"2002","journal-title":"IEEE International High Level Design Validation and Test Workshop"},{"key":"ref3","author":"collier","year":"1992","journal-title":"Reasoning About Parallel Architectures"},{"key":"ref6","doi-asserted-by":"crossref","DOI":"10.1145\/325096.325102","article-title":"Memory consistency and event ordering in scalable shared memory multiprocessors","author":"gharachorloo","year":"1990","journal-title":"Annual International Symposium on Computer Architecture"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.1999.761162"},{"key":"ref8","first-page":"96","article-title":"Multiprocessor validation of the PentiumPro microprocessor","author":"marr","year":"1996","journal-title":"COMPCON"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1979.1675439"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/71.242161"},{"key":"ref1","article-title":"Information-flow models for shared memory with an application to the PowerPC architecture","author":"adir","year":"1998","journal-title":"Technical Report 88 381"},{"key":"ref9","author":"may","year":"1994","journal-title":"The PowerPC Architecture"}],"event":{"name":"IEEE International High Level Design Validation and Test Workshop (HLDVT'02)","location":"Cannes, France","acronym":"HLDVT-02"},"container-title":["Seventh IEEE International High-Level Design Validation and Test Workshop, 2002."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8669\/27468\/01224432.pdf?arnumber=1224432","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,15]],"date-time":"2017-06-15T20:57:31Z","timestamp":1497560251000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1224432\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/hldvt.2002.1224432","relation":{},"subject":[]}}