{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,6]],"date-time":"2025-05-06T04:45:48Z","timestamp":1746506748335},"reference-count":26,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/hldvt.2002.1224436","type":"proceedings-article","created":{"date-parts":[[2003,10,1]],"date-time":"2003-10-01T10:56:02Z","timestamp":1065005762000},"page":"99-103","source":"Crossref","is-referenced-by-count":17,"title":["Automatic functional test program generation for pipelined processors using model checking"],"prefix":"10.1109","author":[{"given":"P.","family":"Mishra","sequence":"first","affiliation":[]},{"given":"N.","family":"Dutt","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","article-title":"Microprocessor design verification using reverse engineering","author":"hauke","year":"1999","journal-title":"HLDVT"},{"key":"ref11","article-title":"Formal verification of superscalar microprocessors with multicycle functional units, exceptions, and branch prediction","author":"velev","year":"2000","journal-title":"DAC"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICFEM.1998.730569"},{"key":"ref13","article-title":"Trace table based approach for pipelined microprocessor verification","author":"sawada","year":"1997","journal-title":"CAV"},{"key":"ref14","article-title":"Formal verification of out-of-. order execution using incremental 'flushing","author":"skakkebaek","year":"1998","journal-title":"CAV"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/52.57892"},{"key":"ref16","doi-asserted-by":"crossref","first-page":"256","DOI":"10.1145\/500001.500061","article-title":"functional abstraction driven design space exploration of heterogeneous programmable architectures","author":"mishra","year":"2001","journal-title":"International Symposium on System Synthesis (IEEE Cat No 01EX526) ISSS-01"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/EURMIC.1999.794466"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2001.915026"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1980.1675602"},{"key":"ref4","article-title":"Automatic verification of pipelined microprocessor control","author":"burch","year":"1994","journal-title":"CAV"},{"key":"ref3","article-title":"Automatic test pattern generation for pipelined processors","author":"iwashita","year":"1994","journal-title":"ICCAD"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/288548.289082"},{"key":"ref5","article-title":"Microprocessor verification in pvs: A methodology and simple example","author":"cyrluk","year":"1993","journal-title":"Technical report SRI-CSL-93–12"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2002.998247"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2002.994963"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.2000.843853"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/978-0-387-35599-3_9"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/307418.307549"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1999.766644"},{"journal-title":"Computer Architecture A Quantitative Approach","year":"1990","author":"hennessy","key":"ref22"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/309847.309908"},{"key":"ref24","article-title":"Micro architecture coverage directed gen – eration of test programs","author":"ur","year":"1999","journal-title":"DAC"},{"key":"ref23","article-title":"Architecture Description Language driven Functional Test Program Generation for Microprocessors using SMV","author":"mishra","year":"2002","journal-title":"Technical Report CECS-02–12"},{"journal-title":"SMV","year":"0","key":"ref26"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/217474.217542"}],"event":{"name":"IEEE International High Level Design Validation and Test Workshop (HLDVT'02)","acronym":"HLDVT-02","location":"Cannes, France"},"container-title":["Seventh IEEE International High-Level Design Validation and Test Workshop, 2002."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8669\/27468\/01224436.pdf?arnumber=1224436","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,15]],"date-time":"2017-06-15T20:57:31Z","timestamp":1497560251000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1224436\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":26,"URL":"https:\/\/doi.org\/10.1109\/hldvt.2002.1224436","relation":{},"subject":[]}}