{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T09:45:06Z","timestamp":1725615906795},"reference-count":9,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/hldvt.2002.1224437","type":"proceedings-article","created":{"date-parts":[[2003,10,1]],"date-time":"2003-10-01T14:56:02Z","timestamp":1065020162000},"page":"107-110","source":"Crossref","is-referenced-by-count":7,"title":["Accelerated verification of RTL assertions based on satisfiability solvers"],"prefix":"10.1109","author":[{"given":"R.","family":"Fraer","sequence":"first","affiliation":[]},{"given":"S.","family":"Ikram","sequence":"additional","affiliation":[]},{"given":"G.","family":"Kamhi","sequence":"additional","affiliation":[]},{"given":"T.","family":"Leonard","sequence":"additional","affiliation":[]},{"given":"A.","family":"Mokkedem","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","article-title":"Benefits of Bounded Model Checking at an Industrial Setting","author":"copty","year":"2001","journal-title":"CAV"},{"key":"ref3","article-title":"Finding Bugs in an Alpha Microprocessor Using Satisfiability Solvers","author":"bjesse","year":"2001","journal-title":"CAV"},{"key":"ref6","article-title":"SAT-based Verification without State Space Traversal","author":"bjesse","year":"2000","journal-title":"FMCAD"},{"key":"ref5","article-title":"Checking Safety Properties Using Induction and a SAT-Solver","author":"sheeran","year":"2000","journal-title":"FMCAD"},{"key":"ref8","article-title":"Assertions Targeting A Diverse Set of Verification Tools","author":"foster","year":"2001","journal-title":"HDLCon2000"},{"key":"ref7","article-title":"Adding Design Assertion Extensions to Verilog","author":"flake","year":"2002","journal-title":"HDLCon2000"},{"key":"ref2","article-title":"Symbolic Model Checking without BDDs","author":"biere","year":"1999","journal-title":"TACAS"},{"article-title":"Principles of Verifiable RTL Design &#x2013; A Functional Coding Style Supporting Verification Processes","year":"2001","author":"bening","key":"ref9"},{"article-title":"Symbolic Model Checking","year":"1993","author":"mcmillan","key":"ref1"}],"event":{"name":"IEEE International High Level Design Validation and Test Workshop (HLDVT'02)","acronym":"HLDVT-02","location":"Cannes, France"},"container-title":["Seventh IEEE International High-Level Design Validation and Test Workshop, 2002."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8669\/27468\/01224437.pdf?arnumber=1224437","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T18:30:38Z","timestamp":1489429838000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1224437\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/hldvt.2002.1224437","relation":{},"subject":[]}}