{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T00:25:16Z","timestamp":1761611116919,"version":"3.28.0"},"reference-count":10,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/hldvt.2002.1224438","type":"proceedings-article","created":{"date-parts":[[2003,10,1]],"date-time":"2003-10-01T14:56:02Z","timestamp":1065020162000},"page":"111-114","source":"Crossref","is-referenced-by-count":6,"title":["Alignability equivalence of synchronous sequential circuits"],"prefix":"10.1109","author":[{"given":"A.","family":"Rosenmann","sequence":"first","affiliation":[]},{"given":"Z.","family":"Hanna","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1996.510841"},{"key":"ref3","first-page":"381","article-title":"A new approach for initialization sequences computation for synchronous sequential circuits","author":"como","year":"1997","journal-title":"IEEE Int Conf on VLSI in Computers and Processors"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/12.280804"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/HLDVT.2001.972825"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1996.510863"},{"key":"ref8","first-page":"376","article-title":"Calculating resetability and reset sequences","author":"pixley","year":"1991","journal-title":"Proc Int Conf Computer-Aided Design"},{"key":"ref7","first-page":"131","article-title":"Divide and conquer combinational logic equivalence verification with false negative elimination","volume":"2102","author":"moondanos","year":"0","journal-title":"CAV 2001"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/103516.103519"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/43.298038"},{"key":"ref1","article-title":"A proof engine approach to solving combinational design automation problems","author":"andersen","year":"2002","journal-title":"Proc of DAC"}],"event":{"name":"IEEE International High Level Design Validation and Test Workshop (HLDVT'02)","acronym":"HLDVT-02","location":"Cannes, France"},"container-title":["Seventh IEEE International High-Level Design Validation and Test Workshop, 2002."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8669\/27468\/01224438.pdf?arnumber=1224438","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T18:41:06Z","timestamp":1489430466000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1224438\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/hldvt.2002.1224438","relation":{},"subject":[]}}