{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T07:18:30Z","timestamp":1729667910436,"version":"3.28.0"},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/hldvt.2005.1568813","type":"proceedings-article","created":{"date-parts":[[2006,1,18]],"date-time":"2006-01-18T18:42:54Z","timestamp":1137609774000},"page":"52-59","source":"Crossref","is-referenced-by-count":4,"title":["VERISEC: VERIfying equivalence of SEquential Circuits using SAT"],"prefix":"10.1109","author":[{"given":"M.","family":"Syal","sequence":"first","affiliation":[]},{"given":"M.S.","family":"Hsiao","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2002.1012640"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.2001.902656"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.1998.655922"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2003.1219042"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382630"},{"year":"0","key":"14"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1023\/A:1011276507260"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2001.156198"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/43.184840"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/43.180261"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/43.908455"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2002.998262"},{"key":"7","doi-asserted-by":"crossref","first-page":"686","DOI":"10.1109\/TCAD.2003.811446","article-title":"On the Verification of Sequential Equivalence","volume":"22","author":"hong","year":"2003","journal-title":"IEEE Trans on CAD of Integrated Circuits and Systems"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1990.129860"},{"key":"5","article-title":"Verification of Synchronous Sequential Machines Based on Symbolic Execution","author":"coudert","year":"1990","journal-title":"LNCS"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1145\/375977.376022"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2001.156196"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/12.769433"}],"event":{"name":"Tenth IEEE International High-Level Design Validation and Test Workshop, 2005.","location":"Napa Valley, CA, USA"},"container-title":["Tenth IEEE International High-Level Design Validation and Test Workshop, 2005."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/10490\/33246\/01568813.pdf?arnumber=1568813","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T22:30:11Z","timestamp":1497652211000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1568813\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/hldvt.2005.1568813","relation":{},"subject":[]}}