{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T15:07:24Z","timestamp":1729609644305,"version":"3.28.0"},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007]]},"DOI":"10.1109\/hldvt.2007.4392781","type":"proceedings-article","created":{"date-parts":[[2008,7,21]],"date-time":"2008-07-21T21:16:34Z","timestamp":1216674994000},"page":"29-36","source":"Crossref","is-referenced-by-count":0,"title":["Automatic TLM generation for C-Based MPSoC design"],"prefix":"10.1109","author":[{"family":"Lucky Lo Chi Yu Lo","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Samar Abdi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"O S Initiative Systemc","year":"0","key":"ref10"},{"key":"ref11","article-title":"Automatic generation of scheduled systemc models of embedded systems from extended task graphs","author":"klaus","year":"2002","journal-title":"Proc Int Forum onDesign Languages"},{"journal-title":"U of California-Berkeley The ptolemy project","year":"0","key":"ref12"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2003.1253825"},{"key":"ref14","doi-asserted-by":"crossref","first-page":"1523","DOI":"10.1109\/43.898830","article-title":"System level design: Orthogonalization of concerns and platform-based design","volume":"19","author":"sangiovanni-vicentelli","year":"2000","journal-title":"IEEE Transactions on Computer-Aided Design of Circuits and Systems"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/IWRSP.2004.1311101"},{"journal-title":"Generic modeling environment","year":"0","key":"ref16"},{"journal-title":"CoWare N2C","year":"0","key":"ref4"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1155\/2007\/75373"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1016720.1016742"},{"journal-title":"Platform Architect","year":"0","key":"ref5"},{"key":"ref8","first-page":"560","article-title":"Design for verification of systemc transaction level models","author":"rabibi","year":"2005","journal-title":"DATE '05 Proceedings of the conference on Design Automation and Test in Europe"},{"journal-title":"System Design with SystemC","year":"2002","author":"grotker","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/944645.944651"},{"key":"ref1","article-title":"Systemc code generation from uml model","author":"bruschi","year":"2003","journal-title":"Proc Forum Specification & Design Languages FDL"},{"key":"ref9","article-title":"Automatic generation of executable modesl from structured approach real-time specifications","author":"hastono","year":"2004","journal-title":"Proceedings of the 25th IEEE International Real-Time Systems Symposium (RTSS)"}],"event":{"name":"2007 IEEE International High Level Design Validation and Test Workshop","start":{"date-parts":[[2007,11,7]]},"location":"Irvine, CA, USA","end":{"date-parts":[[2007,11,9]]}},"container-title":["2007 IEEE International High Level Design Validation and Test Workshop"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4392771\/4392772\/04392781.pdf?arnumber=4392781","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,18]],"date-time":"2017-06-18T10:10:21Z","timestamp":1497780621000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4392781\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/hldvt.2007.4392781","relation":{},"subject":[],"published":{"date-parts":[[2007]]}}}