{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T06:11:26Z","timestamp":1729663886949,"version":"3.28.0"},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007]]},"DOI":"10.1109\/hldvt.2007.4392794","type":"proceedings-article","created":{"date-parts":[[2008,7,21]],"date-time":"2008-07-21T17:16:34Z","timestamp":1216660594000},"page":"97-104","source":"Crossref","is-referenced-by-count":4,"title":["A novel formal approach to generate high-level test vectors without ILP and SAT solvers"],"prefix":"10.1109","author":[{"given":"Bijan","family":"Alizadeh","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Masahiro","family":"Fujita","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/225871.225880"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1998.743202"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.1997.600304"},{"key":"ref6","first-page":"120","article-title":"Smart Simulation using Collaborative Formal and Simulation Engines","author":"ho","year":"2000","journal-title":"Proceedings of ICCAD"},{"key":"ref11","first-page":"298","article-title":"A Hybrid Approach for Equivalence Checking between System Level and RTL Descriptions","author":"alizadeh","year":"2007","journal-title":"Int Workshop Logic Synthesis"},{"key":"ref5","first-page":"385","article-title":"Enhancing Simulation with BDDs and ATPGs","author":"ganai","year":"1999","journal-title":"Proceedings of Design Automation Conference (DAC)"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/98.972168"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/43.913756"},{"key":"ref7","doi-asserted-by":"crossref","first-page":"528","DOI":"10.1145\/277044.277187","article-title":"Functional vector generation for HDL models using linear programming and 3-satisfiability","author":"fallah","year":"1998","journal-title":"Proceedings 1998 Design and Automation Conference 35th DAC (Cat No 98CH36175) DAC"},{"article-title":"Coverage Directed Validation of Hardware Models","year":"1999","author":"fallah","key":"ref2"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"488","DOI":"10.1016\/j.sysarc.2004.10.006","article-title":"Functional Test Generation based on Word-level SAT","volume":"51","author":"zeng","year":"2005","journal-title":"Elsevier Journal of Systems Architecture"},{"key":"ref1","first-page":"15","article-title":"LTED: A Canonical and Compact Hybrid Word-Boolean Representation as a Formal Model for Hardware\/Software Co-designs","author":"alizadeh","year":"2007","journal-title":"International Workshop on Constraints in Formal Verification (CFV07)"}],"event":{"name":"2007 IEEE International High Level Design Validation and Test Workshop","start":{"date-parts":[[2007,11,7]]},"location":"Irvine, CA, USA","end":{"date-parts":[[2007,11,9]]}},"container-title":["2007 IEEE International High Level Design Validation and Test Workshop"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4392771\/4392772\/04392794.pdf?arnumber=4392794","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,18]],"date-time":"2017-06-18T06:10:21Z","timestamp":1497766221000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4392794\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/hldvt.2007.4392794","relation":{},"subject":[],"published":{"date-parts":[[2007]]}}}