{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T03:17:15Z","timestamp":1729653435837,"version":"3.28.0"},"reference-count":23,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,11]]},"DOI":"10.1109\/hldvt.2008.4695865","type":"proceedings-article","created":{"date-parts":[[2008,12,10]],"date-time":"2008-12-10T16:43:50Z","timestamp":1228927430000},"page":"3-10","source":"Crossref","is-referenced-by-count":1,"title":["Positioning test-benches and test-programs in interaction-oriented system-on-chip verification"],"prefix":"10.1109","author":[{"given":"Xiaoxi","family":"Xu","sequence":"first","affiliation":[]},{"given":"Cheng-Chew","family":"Lim","sequence":"additional","affiliation":[]},{"given":"Michael","family":"Liebelt","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Nios Hardware Development Tutorial ver 1 2","year":"2004","key":"19"},{"key":"22","first-page":"12","author":"milner","year":"1989","journal-title":"Communication and Concurrency"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1007\/11678779_1"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.923092"},{"key":"18","doi-asserted-by":"crossref","first-page":"149","DOI":"10.1109\/HLDVT.2003.1252489","article-title":"scheduling of transactions for system level testcase generation","author":"emek","year":"2003","journal-title":"Proc 7th Ann IEEE Int l High-Level Design Validation and Test Workshop"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065789"},{"journal-title":"Architecture for Simulation Testbench Control","year":"2003","author":"johns","key":"16"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/VLSISOC.2006.313211"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/APCCAS.2006.342151"},{"journal-title":"Unified Verification of SoC Hardware and Embedded Software","year":"2007","author":"andrews","key":"11"},{"journal-title":"Using a Processor-driven Test Bench for Functional Verification of Embedded SoCs","year":"0","author":"kenney","key":"12"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1145\/944645.944651"},{"journal-title":"Transaction-Based Verification in HDL","year":"0","key":"3"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/EPEP.2007.4387151"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065714"},{"key":"1","article-title":"practical approaches to soc verification","author":"mosensoson","year":"2002","journal-title":"Proceedings of DATE User Forum"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/HLDVT.2002.1224444"},{"key":"7","article-title":"verification languages and where they fit","volume":"11","author":"bailey","year":"2003","journal-title":"Proceedings of EdaForum 2003"},{"key":"6","article-title":"systemverilog reference verification methodology: rtl","author":"anderson","year":"2006","journal-title":"EETimes Design News"},{"journal-title":"SoC Verification A Layered Testbench Architecture A System for Regression Management A Coverage Methodology","year":"2003","author":"karppanen","key":"5"},{"journal-title":"Ten 2008 Trends in System and Chip Design","year":"2008","author":"goering","key":"4"},{"key":"9","doi-asserted-by":"crossref","DOI":"10.1109\/HLDVT.2002.1224425","article-title":"top-level validation of system-on-chip in esterel studio","author":"berry","year":"2002","journal-title":"HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop"},{"key":"8","first-page":"586","article-title":"verifying system-on-chips at the software application level","author":"cheng","year":"2005","journal-title":"Proceedings of IFIP-WG Conference on Very Large Scale Integration System-on-Chip"}],"event":{"name":"2008 IEEE International High Level Design Validation and Test Workshop (HLDVT)","start":{"date-parts":[[2008,11,19]]},"location":"Incline Village, NV, USA","end":{"date-parts":[[2008,11,21]]}},"container-title":["2008 IEEE International High Level Design Validation and Test Workshop"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4690895\/4695856\/04695865.pdf?arnumber=4695865","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,16]],"date-time":"2019-05-16T04:20:46Z","timestamp":1557980446000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4695865\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,11]]},"references-count":23,"URL":"https:\/\/doi.org\/10.1109\/hldvt.2008.4695865","relation":{},"subject":[],"published":{"date-parts":[[2008,11]]}}}