{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,3]],"date-time":"2024-09-03T19:35:01Z","timestamp":1725392101022},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,11]]},"DOI":"10.1109\/hldvt.2008.4695882","type":"proceedings-article","created":{"date-parts":[[2008,12,10]],"date-time":"2008-12-10T11:43:50Z","timestamp":1228909430000},"page":"85-92","source":"Crossref","is-referenced-by-count":0,"title":["Functional testing approaches for “BIFST-able” tlm_fifo"],"prefix":"10.1109","author":[{"given":"H.","family":"Alemzadeh","sequence":"first","affiliation":[]},{"given":"Z.","family":"Navabi","sequence":"additional","affiliation":[]},{"given":"S.","family":"Di Carlo","sequence":"additional","affiliation":[]},{"given":"A.","family":"Scionti","sequence":"additional","affiliation":[]},{"given":"P.","family":"Prinetto","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"17","DOI":"10.1109\/ATS.1992.224443"},{"doi-asserted-by":"publisher","key":"18","DOI":"10.1109\/EDAC.1993.386425"},{"doi-asserted-by":"publisher","key":"15","DOI":"10.1109\/VTS.2002.1011171"},{"doi-asserted-by":"publisher","key":"16","DOI":"10.1145\/304065.304099"},{"year":"1991","author":"van de goor","journal-title":"Testing Semiconductor Memories Theory and Practice","key":"13"},{"doi-asserted-by":"publisher","key":"14","DOI":"10.1109\/DATE.2001.915069"},{"key":"11","article-title":"application area specific system level fault models: a case study with a simple noc switch","author":"bengtsson","year":"2006","journal-title":"International Design and Test Workshop (IDT)"},{"doi-asserted-by":"publisher","key":"12","DOI":"10.1109\/ATS.2007.97"},{"year":"2008","journal-title":"OSCI SystemC TLM 2 0 Standard","key":"3"},{"year":"2007","author":"pezze?","journal-title":"Software Testing and Analysis Process Principles and Techniques","key":"2"},{"doi-asserted-by":"publisher","key":"1","DOI":"10.1109\/TEST.2008.4700610"},{"doi-asserted-by":"publisher","key":"10","DOI":"10.1109\/DFTVS.1996.572028"},{"doi-asserted-by":"publisher","key":"7","DOI":"10.1109\/TC.1984.1676471"},{"key":"6","first-page":"990","article-title":"native mode functional test generation for processors with applications to self test and design validation","author":"shen","year":"1998","journal-title":"Proc of International Test Conference"},{"doi-asserted-by":"publisher","key":"5","DOI":"10.1109\/HLDVT.2001.972822"},{"year":"2004","author":"rose","journal-title":"Transaction Level Modelling in SystemC OSCI White-paper","key":"4"},{"doi-asserted-by":"publisher","key":"9","DOI":"10.1109\/MT.1993.263146"},{"doi-asserted-by":"publisher","key":"8","DOI":"10.1109\/TEST.1992.527890"}],"event":{"name":"2008 IEEE International High Level Design Validation and Test Workshop (HLDVT)","start":{"date-parts":[[2008,11,19]]},"location":"Incline Village, NV, USA","end":{"date-parts":[[2008,11,21]]}},"container-title":["2008 IEEE International High Level Design Validation and Test Workshop"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4690895\/4695856\/04695882.pdf?arnumber=4695882","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,17]],"date-time":"2017-03-17T13:54:42Z","timestamp":1489758882000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4695882\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,11]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/hldvt.2008.4695882","relation":{},"subject":[],"published":{"date-parts":[[2008,11]]}}}