{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T16:09:49Z","timestamp":1725725389186},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,11]]},"DOI":"10.1109\/hldvt.2009.5340181","type":"proceedings-article","created":{"date-parts":[[2009,12,10]],"date-time":"2009-12-10T10:27:48Z","timestamp":1260440868000},"page":"20-25","source":"Crossref","is-referenced-by-count":9,"title":["MCBCG: Model Checking Based Sequential Clock-Gating"],"prefix":"10.1109","author":[{"given":"Sumit","family":"Ahuja","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sandeep","family":"Shukla","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/MSE.2005.8"},{"journal-title":"VCS Comprehensive RTL Verification Solution","year":"0","key":"15"},{"year":"0","key":"16"},{"key":"13","first-page":"230","article-title":"A novel sequential circuit optimization with clock gating logic","author":"kuo","year":"2008","journal-title":"ICCAD '08 Proceedings of the 2008 IEEE\/ACM International Conference on Computer-Aided Design"},{"year":"0","key":"14"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1145\/1013235.1013248"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2001.937451"},{"journal-title":"Frank Emnett and Mark Biegel","year":"0","key":"3"},{"year":"0","key":"2"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-5433-2"},{"journal-title":"A System for Sequential Synthesis and Verification","year":"0","key":"10"},{"journal-title":"Clock Gating for Power Optimization in ASIC","year":"0","author":"ramesh","key":"7"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1268895"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2003.1183529"},{"journal-title":"The Power of RTL Clock-gating","year":"0","author":"dale","key":"4"},{"journal-title":"Verification Interacting with Synthesis (VIS)","year":"0","key":"9"},{"journal-title":"The Cadence SMV Model Checker","year":"0","key":"8"}],"event":{"name":"2009 IEEE International High Level Design Validation and Test Workshop (HLDVT)","start":{"date-parts":[[2009,11,4]]},"location":"San Francisco, CA, USA","end":{"date-parts":[[2009,11,6]]}},"container-title":["2009 IEEE International High Level Design Validation and Test Workshop"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5331931\/5340157\/05340181.pdf?arnumber=5340181","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,18]],"date-time":"2017-03-18T21:10:16Z","timestamp":1489871416000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5340181\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,11]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/hldvt.2009.5340181","relation":{},"subject":[],"published":{"date-parts":[[2009,11]]}}}