{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T03:15:00Z","timestamp":1729653300135,"version":"3.28.0"},"reference-count":37,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,6]]},"DOI":"10.1109\/hldvt.2010.5496644","type":"proceedings-article","created":{"date-parts":[[2010,7,6]],"date-time":"2010-07-06T14:06:27Z","timestamp":1278425187000},"page":"154-159","source":"Crossref","is-referenced-by-count":1,"title":["Verification of real-time properties for Hardware-dependent Software"],"prefix":"10.1109","author":[{"given":"Wolfgang","family":"Mueller","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marcio F.","family":"da S. Oliveira","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Henning","family":"Zabel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Markus","family":"Becker","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","article-title":"Formal Methods for System Level Performance Analysis and Optimization","author":"schliecker","year":"2008","journal-title":"Proc of the Design Verification Conference (DVCON)"},{"key":"ref32","article-title":"Fast and Accurate Transaction Level Models using Result Oriented Modeling","author":"schirner","year":"2006","journal-title":"Int Conf Comput -Aided Design"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2007.358016"},{"key":"ref30","article-title":"RTOS modeling","volume":"10","author":"posadas","year":"2007","journal-title":"SystemC for Real-Time Embedded SW Simulation A POSIX Model Design Automation for Embedded Systems"},{"journal-title":"IFIP Conference on Distributed and Parallel Embedded Systems (DIPES)","year":"2008","author":"zabel","key":"ref37"},{"key":"ref36","article-title":"Noise injection in abstract RTOS Simulation in SystemC","author":"zabel","year":"2009","journal-title":"Proc of the Design Automation and Test in Europe (DATE)"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4020-9436-1_9"},{"key":"ref34","article-title":"Fast and Accurate Cosimulation of MPSoC Using Trace-Driven Virtual Synchronization","volume":"7","author":"yi","year":"2007","journal-title":"IEEE Trans on CAD of Integrated Circuits and Systems"},{"key":"ref10","article-title":"Using transactional level models in a SoC design flow","author":"clouard","year":"2003","journal-title":"SystemC - Methodologies and Applications"},{"key":"ref11","article-title":"A Smooth Refinement Flow for CodesigningHW and SW Threads","author":"destro","year":"2007","journal-title":"Proc of the Design Automation and Test in Europe (DATE)"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4020-9436-1_1"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2003.1253598"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/b137175"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4020-6254-4_19"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/1629435.1629446"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.263"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/1403375.1403380"},{"journal-title":"IEEE Computer Society","year":"2005","key":"ref19"},{"key":"ref4","first-page":"41","article-title":"QEMU, a fast and portable dynamic translator","author":"bellard","year":"2005","journal-title":"Proc of the USENIX Annual Technical Conference"},{"journal-title":"OSCI TLM-2 0 Language Reference Manual","year":"2009","key":"ref28"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-15234-4_15"},{"journal-title":"OSCI Transaction Level Modeling Library Release 1 0","year":"2005","key":"ref27"},{"journal-title":"VMM for SystemVerilog","year":"2005","author":"bergeron","key":"ref6"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-0302-6"},{"journal-title":"OVM Open Verification Methodology","year":"2005","key":"ref29"},{"key":"ref8","article-title":"Transaction Level Modeling: An Overview","author":"cai","year":"2003","journal-title":"Proc Int Conf Hardware\/Software Codesign System Synthesis"},{"journal-title":"Hard Real-Time Computing Systems Predictable Scheduling Algorithms and Applications","year":"1997","author":"buttazo","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5456965"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2003.1253607"},{"journal-title":"Open Verification Library","year":"0","key":"ref1"},{"journal-title":"IEEE Computer Society","year":"2005","key":"ref20"},{"journal-title":"IEEE Computer Society","year":"2006","key":"ref22"},{"journal-title":"IEEE Computer Society","year":"2008","key":"ref21"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/REAL.1990.128748"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/DTIS.2006.1708698"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5457130"},{"key":"ref25","doi-asserted-by":"crossref","DOI":"10.1109\/DAC.2002.1012588","article-title":"A Universal Technique for Fast and Flexible Instruction-Set Architecture Simulation","author":"nohl","year":"2002","journal-title":"Proc of Design Automation Conference (DAC)"}],"event":{"name":"2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)","start":{"date-parts":[[2010,6,10]]},"location":"Anaheim, FL, USA","end":{"date-parts":[[2010,6,12]]}},"container-title":["2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5488975\/5496643\/05496644.pdf?arnumber=5496644","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,19]],"date-time":"2017-06-19T06:25:29Z","timestamp":1497853529000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5496644\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,6]]},"references-count":37,"URL":"https:\/\/doi.org\/10.1109\/hldvt.2010.5496644","relation":{},"subject":[],"published":{"date-parts":[[2010,6]]}}}