{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T18:10:38Z","timestamp":1729620638014,"version":"3.28.0"},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,6]]},"DOI":"10.1109\/hldvt.2010.5496654","type":"proceedings-article","created":{"date-parts":[[2010,7,6]],"date-time":"2010-07-06T14:06:27Z","timestamp":1278425187000},"page":"97-102","source":"Crossref","is-referenced-by-count":0,"title":["Fast and accurate UML State Chart modeling using TLM&lt;sup&gt;&amp;#x002B;&lt;\/sup&gt; control flow abstraction"],"prefix":"10.1109","author":[{"given":"Rainer","family":"Findenig","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Thomas","family":"Leitner","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael","family":"Veiten","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wolfgang","family":"Ecker","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-31862-0_15"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/REAL.2004.32"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1228784.1228904"},{"key":"ref13","doi-asserted-by":"crossref","first-page":"227","DOI":"10.1007\/978-1-4020-8297-9_16","article-title":"SC2 StateCharts to SystemC: Automatic Executable Models Generation","author":"mura","year":"2008","journal-title":"Embedded Systems Specification and Design Languages"},{"key":"ref14","first-page":"915","article-title":"A model-driven design environment for embedded systems","author":"riccobene","year":"0","journal-title":"San Francisco CA USA ACM 2006 Conference proceedings"},{"key":"ref15","first-page":"13","article-title":"Transaction-Level State Charts in UML and SystemC with zero-time evaluation","author":"findenig","year":"2010","journal-title":"Design & Verification Conference & Exhibition (DVCon)"},{"journal-title":"aSCI TLM-2 0 Language Reference Manual","year":"2009","key":"ref16"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5457234"},{"key":"ref18","first-page":"1","article-title":"Defining TLM+","author":"ecker","year":"2010","journal-title":"Design & Verification Conference & Exhibition (DVCon)"},{"journal-title":"OMG Unified Modeling Language Superstructure Version 2 2","year":"2009","key":"ref4"},{"key":"ref3","first-page":"325","author":"harel","year":"2001","journal-title":"The Rhapsody Semantics of Statecharts (or On the Executable Core of the UML)"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"415","DOI":"10.1007\/s10270-006-0042-8","article-title":"UML vs. classical vs. rhapsody statecharts: not all models are created equal","volume":"6","author":"crane","year":"2007","journal-title":"Software & Systems Modeling"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"128","DOI":"10.1007\/3-540-58468-4_163","article-title":"A comparison of statecharts variants","author":"von der beeck","year":"1994","journal-title":"Formal Techniques in Real-Time and Fault-Tolerant Systems"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/s001659970003"},{"key":"ref7","first-page":"90","article-title":"Implementing statecharts in PROMELA\/SPIN","author":"mikk","year":"1998"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/235321.235322"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1016\/0167-6423(87)90035-9"},{"key":"ref9","first-page":"282","author":"qin","year":"2003","journal-title":"Mapping Statecharts to Verilog for Hardware\/Software Co-specification"}],"event":{"name":"2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)","start":{"date-parts":[[2010,6,10]]},"location":"Anaheim, FL, USA","end":{"date-parts":[[2010,6,12]]}},"container-title":["2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5488975\/5496643\/05496654.pdf?arnumber=5496654","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,19]],"date-time":"2017-06-19T06:25:29Z","timestamp":1497853529000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5496654\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,6]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/hldvt.2010.5496654","relation":{},"subject":[],"published":{"date-parts":[[2010,6]]}}}