{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T10:21:44Z","timestamp":1725618104218},"reference-count":21,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,11]]},"DOI":"10.1109\/hldvt.2011.6114164","type":"proceedings-article","created":{"date-parts":[[2012,1,6]],"date-time":"2012-01-06T19:31:55Z","timestamp":1325878315000},"page":"41-48","source":"Crossref","is-referenced-by-count":4,"title":["A scalable hybrid verification system based on HDL slicing"],"prefix":"10.1109","author":[{"given":"Somnath","family":"Banerjee","sequence":"first","affiliation":[]},{"given":"Tushar","family":"Gupta","sequence":"additional","affiliation":[]},{"given":"Saurabh","family":"Jain","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"crossref","first-page":"164","DOI":"10.1145\/277044.277083","article-title":"Enhanced visibility and performance in functional verification by reconstruction","author":"marantz","year":"1998","journal-title":"Proceedings 1998 Design and Automation Conference 35th DAC (Cat No 98CH36175) DAC"},{"doi-asserted-by":"publisher","key":"17","DOI":"10.1109\/VLSID.2007.70"},{"key":"18","first-page":"154","article-title":"An automatic circuit extractor for RTL verification","author":"li","year":"2003","journal-title":"Test Symposium 2003 ATS 2003 12th Asian"},{"doi-asserted-by":"publisher","key":"15","DOI":"10.1109\/MWSCAS.2006.382105"},{"doi-asserted-by":"publisher","key":"16","DOI":"10.1109\/TEST.2006.297665"},{"doi-asserted-by":"publisher","key":"13","DOI":"10.1109\/32.83912"},{"doi-asserted-by":"publisher","key":"14","DOI":"10.1109\/TC.1981.1675757"},{"doi-asserted-by":"publisher","key":"11","DOI":"10.1109\/TSE.1984.5010248"},{"doi-asserted-by":"publisher","key":"12","DOI":"10.1145\/358557.358577"},{"doi-asserted-by":"publisher","key":"21","DOI":"10.1109\/ASQED.2009.5206235"},{"doi-asserted-by":"publisher","key":"3","DOI":"10.1109\/IWRSP.1999.779047"},{"doi-asserted-by":"publisher","key":"20","DOI":"10.1109\/71.730527"},{"doi-asserted-by":"publisher","key":"2","DOI":"10.1109\/43.640619"},{"doi-asserted-by":"publisher","key":"1","DOI":"10.1109\/ICCD.1992.276356"},{"doi-asserted-by":"publisher","key":"10","DOI":"10.1109\/92.820760"},{"doi-asserted-by":"publisher","key":"7","DOI":"10.1109\/MDT.2007.46"},{"doi-asserted-by":"publisher","key":"6","DOI":"10.1109\/ATS.2004.15"},{"doi-asserted-by":"publisher","key":"5","DOI":"10.1109\/TEST.2000.894203"},{"doi-asserted-by":"publisher","key":"4","DOI":"10.1109\/WSC.2001.977471"},{"doi-asserted-by":"publisher","key":"9","DOI":"10.1109\/ICCAD.1997.643403"},{"doi-asserted-by":"publisher","key":"8","DOI":"10.1109\/43.806800"}],"event":{"name":"2011 IEEE International High Level Design Validation and Test Workshop (HLDVT)","start":{"date-parts":[[2011,11,9]]},"location":"Napa Valley, CA, USA","end":{"date-parts":[[2011,11,11]]}},"container-title":["2011 IEEE International High Level Design Validation and Test Workshop"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6093762\/6113979\/06114164.pdf?arnumber=6114164","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,20]],"date-time":"2017-06-20T12:22:55Z","timestamp":1497961375000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6114164\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,11]]},"references-count":21,"URL":"https:\/\/doi.org\/10.1109\/hldvt.2011.6114164","relation":{},"subject":[],"published":{"date-parts":[[2011,11]]}}}