{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,2]],"date-time":"2026-06-02T13:19:05Z","timestamp":1780406345892,"version":"3.54.1"},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,10]]},"DOI":"10.1109\/hldvt.2016.7748248","type":"proceedings-article","created":{"date-parts":[[2016,11,22]],"date-time":"2016-11-22T02:23:51Z","timestamp":1479781431000},"page":"1-8","source":"Crossref","is-referenced-by-count":3,"title":["Synthesizable SVA protocol checker generation methodology based on TDML and VCD file formats"],"prefix":"10.1109","author":[{"given":"Mohamed O.","family":"Kayed","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mohamed","family":"Abdelsalam","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Rafik","family":"Guindi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref4","first-page":"209","article-title":"Low Power Double Data Rate 3 (LPDDR3)","year":"2012","journal-title":"JEDEC Solid state Technology Association"},{"key":"ref3","article-title":"Synopsys ZeBu Server","year":"0"},{"key":"ref10","article-title":"A Novel Approach for SVA Generation of DDR Memory Protocols Bas ed on TDML","author":"kayed","year":"2014","journal-title":"15th MTV Workshop"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/LATW.2013.6562663"},{"key":"ref11","article-title":"TDML Website","year":"0"},{"key":"ref5","article-title":"Message Sequence Charts for Assertion-based Verification","author":"lee","year":"2013","journal-title":"CECS Technical Report"},{"key":"ref12","year":"2006"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"545","DOI":"10.1145\/1403375.1403506","article-title":"Automatic generation of complex properties for hardware designs","author":"rogin","year":"2008","journal-title":"Proc of the Conf on Design Automation and Test in Europe"},{"key":"ref7","article-title":"UML to SystemVerilog synthesis for embedded system models with support for assertion generation","author":"li","year":"2007","journal-title":"Proc of the Forum on Design Languages"},{"key":"ref2","article-title":"Mentor Graphics Veloce Emulation Platform","year":"0"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5457129"},{"key":"ref1","year":"0"}],"event":{"name":"2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)","location":"Santa Cruz, CA, USA","start":{"date-parts":[[2016,10,7]]},"end":{"date-parts":[[2016,10,8]]}},"container-title":["2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7746774\/7748241\/07748248.pdf?arnumber=7748248","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,14]],"date-time":"2022-07-14T12:24:14Z","timestamp":1657801454000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7748248\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,10]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/hldvt.2016.7748248","relation":{},"subject":[],"published":{"date-parts":[[2016,10]]}}}