{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,3]],"date-time":"2025-10-03T08:55:18Z","timestamp":1759481718856},"reference-count":20,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,10]]},"DOI":"10.1109\/hldvt.2016.7748254","type":"proceedings-article","created":{"date-parts":[[2016,11,21]],"date-time":"2016-11-21T21:23:51Z","timestamp":1479763431000},"source":"Crossref","is-referenced-by-count":26,"title":["Design centric modeling of digital hardware"],"prefix":"10.1109","author":[{"given":"Johannes","family":"Schreiner","sequence":"first","affiliation":[]},{"given":"Rainer","family":"Findenigy","sequence":"additional","affiliation":[]},{"given":"Wolfgang","family":"Ecker","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","year":"0"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2001.915003"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1016\/B978-0-444-81641-2.50038-1"},{"key":"ref13","author":"association","year":"1993","journal-title":"UDL-I Unified Design Language for Integrated Circuits definition UDL\/I Language Reference Manual Version 2 0 3 Translation from the Japanese Language Reference Manual JEIDA"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.81"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2016.11"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228584"},{"key":"ref17","article-title":"Specification for the firrtl language","author":"li","year":"2016","journal-title":"EECS Department University of California Berkeley Tech Rep"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/HLDVT.2010.5496665"},{"key":"ref19","first-page":"65","author":"borrione","year":"1997","journal-title":"An approach to Verilog-VHDL interoperability for synchronous designs"},{"key":"ref4","year":"0"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2016.7753576"},{"key":"ref6","year":"0"},{"key":"ref5","author":"holcombe","year":"0","journal-title":"Algebraic Automata Theory ser Cambridge Studies in Advanced Mathematics"},{"key":"ref8","year":"0"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.1999.761165"},{"key":"ref2","author":"collet","year":"0","journal-title":"(2013 Autumn) McKinsey on Semiconductors What happens when chip-design complexity outpaces development productivity"},{"key":"ref1","author":"robert hum","year":"2016","journal-title":"Submicron Division personal discussion on quantum leaps in design productivity"},{"key":"ref9","year":"0","journal-title":"Logic Synthesis Using Synopsys 2nd edition"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1016\/S0920-5489(02)00017-X"}],"event":{"name":"2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)","location":"Santa Cruz, CA, USA","start":{"date-parts":[[2016,10,7]]},"end":{"date-parts":[[2016,10,8]]}},"container-title":["2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7746774\/7748241\/07748254.pdf?arnumber=7748254","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2016,12,7]],"date-time":"2016-12-07T12:34:34Z","timestamp":1481114074000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7748254\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,10]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/hldvt.2016.7748254","relation":{},"subject":[],"published":{"date-parts":[[2016,10]]}}}