{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T07:47:09Z","timestamp":1725522429461},"reference-count":23,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,10]]},"DOI":"10.1109\/hldvt.2017.8167457","type":"proceedings-article","created":{"date-parts":[[2017,12,7]],"date-time":"2017-12-07T23:32:13Z","timestamp":1512689533000},"page":"9-16","source":"Crossref","is-referenced-by-count":0,"title":["Reachability analysis in RTL circuits using k-induction bounded model checking"],"prefix":"10.1109","author":[{"given":"Tonmoy","family":"Roy","sequence":"first","affiliation":[]},{"given":"Michael","family":"Hsiao","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Verilator","year":"0","key":"ref10"},{"journal-title":"Z3","year":"0","key":"ref11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/390013.808479"},{"journal-title":"Computer Architecture A Quantitative Approach","year":"2003","author":"hennessy","key":"ref13"},{"journal-title":"Software Change Impact Analysis","year":"1996","author":"arnold","key":"ref14"},{"journal-title":"Optimizing Compilers for Modern Architectures A Dependence-Based Approach","year":"2002","author":"kennedy","key":"ref15"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/73560.73561"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/115372.115320"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TSE.1984.5010248"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1023\/A:1011276507260"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/348019.348288"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/EDTC.1997.582325"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2012.6401556"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.1997.568180"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2013.51"},{"key":"ref7","first-page":"1","article-title":"Efficient validation input generation in rtl by hybridized source code analysis","author":"liu","year":"2011","journal-title":"2011 Design, Automation & Test in Europe"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2008.4484714"},{"journal-title":"The 2014 wilson research group functional verification study","year":"2014","author":"foster","key":"ref1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2015.7085434"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ICSICT.2006.306623"},{"key":"ref22","first-page":"127","author":"sheeran","year":"2000","journal-title":"Checking Safety Properties Using Induction and A SAT-solver"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1016\/S1571-0661(05)82542-3"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-23702-7_26"}],"event":{"name":"2017 IEEE International High-Level Design Validation and Test Workshop (HLDVT)","start":{"date-parts":[[2017,10,5]]},"location":"Santa Cruz, CA","end":{"date-parts":[[2017,10,6]]}},"container-title":["2017 IEEE International High Level Design Validation and Test Workshop (HLDVT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8119415\/8167450\/08167457.pdf?arnumber=8167457","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,1,15]],"date-time":"2018-01-15T22:53:45Z","timestamp":1516056825000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8167457\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,10]]},"references-count":23,"URL":"https:\/\/doi.org\/10.1109\/hldvt.2017.8167457","relation":{},"subject":[],"published":{"date-parts":[[2017,10]]}}}