{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,8]],"date-time":"2025-07-08T05:10:03Z","timestamp":1751951403511,"version":"3.41.2"},"reference-count":22,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,5,5]],"date-time":"2025-05-05T00:00:00Z","timestamp":1746403200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,5,5]],"date-time":"2025-05-05T00:00:00Z","timestamp":1746403200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001665","name":"French National Research Agency (ANR)","doi-asserted-by":"publisher","award":["ANR-22-PECY0004"],"award-info":[{"award-number":["ANR-22-PECY0004"]}],"id":[{"id":"10.13039\/501100001665","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,5,5]]},"DOI":"10.1109\/host64725.2025.11050059","type":"proceedings-article","created":{"date-parts":[[2025,7,7]],"date-time":"2025-07-07T17:47:34Z","timestamp":1751910454000},"page":"279-288","source":"Crossref","is-referenced-by-count":0,"title":["On the Impact of Metastability in Jitter Based TRNG"],"prefix":"10.1109","author":[{"given":"Florian","family":"Pebay-Peyroula","sequence":"first","affiliation":[{"name":"Univ. Grenoble Alpes, CEA-Leti,Grenoble,France"}]},{"given":"Licinius-Pompiliu","family":"Benea","sequence":"additional","affiliation":[{"name":"Univ. Grenoble Alpes, CEA-Leti,Grenoble,France"}]},{"given":"Mikael","family":"Carmona","sequence":"additional","affiliation":[{"name":"Univ. Grenoble Alpes, CEA-Leti,Grenoble,France"}]},{"given":"Romain","family":"Wacquez","sequence":"additional","affiliation":[{"name":"CEA-Leti, Mines St-Étienne, Equipe Commune,Gardanne,France"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2016.7577379"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2023.3288036"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2022.3184950"},{"key":"ref4","article-title":"A proposal for functionality classes for random number generators, version 3.0","author":"Peter","year":"2024","journal-title":"Bundesamt fur Sicherheit in der Informationstechnik (BSI). Bonn Sept"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.6028\/NIST.SP.800-90B"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/s00145-010-9089-3"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/s00145-024-09494-6"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-44318-8_12"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/4.766813"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2003.810480"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2007.250627"},{"journal-title":"ST Microelectronics, Introduction to random number generation validation using the NIST statistical test suite for STM32 MCUs and MPUs","year":"2024","key":"ref12"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2019.00041"},{"key":"ref14","article-title":"COSOI: True Random Number Generator Based on Coherent Sampling using the FD-SOI technology","volume":"10","author":"Benea","year":"2024","journal-title":"WiPiEC Journal - Works in Progress in Embedded Computing Journal"},{"key":"ref15","article-title":"Clock domain crossing (CDC) design & verification techniques using SystemVerilog","author":"Cummings","year":"2008","journal-title":"SNUG-2008, Boston"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-38908-5_7"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2018.00090"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-85053-3_11"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1093\/oso\/9780199219858.001.0001"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/DTTIS62212.2024.10780212"},{"key":"ref21","volume":"6","author":"Xilinx","year":"2018","journal-title":"Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics"},{"key":"ref22","article-title":"Reducing delay uncertainty in deeply scaled integrated circuits using interdependent timing constraints","volume-title":"Proc. ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)","author":"Salman","year":"2010"}],"event":{"name":"2025 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","start":{"date-parts":[[2025,5,5]]},"location":"San Jose, CA, USA","end":{"date-parts":[[2025,5,8]]}},"container-title":["2025 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11050019\/11050011\/11050059.pdf?arnumber=11050059","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,8]],"date-time":"2025-07-08T04:46:12Z","timestamp":1751949972000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11050059\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,5,5]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/host64725.2025.11050059","relation":{},"subject":[],"published":{"date-parts":[[2025,5,5]]}}}