{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T10:26:16Z","timestamp":1725618376704},"reference-count":0,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,8]]},"DOI":"10.1109\/hotchips.2014.7478818","type":"proceedings-article","created":{"date-parts":[[2016,7,4]],"date-time":"2016-07-04T21:04:59Z","timestamp":1467666299000},"page":"1-24","source":"Crossref","is-referenced-by-count":1,"title":["Design of a high-density SoC FPGA at 20nm"],"prefix":"10.1109","author":[{"given":"Brad","family":"Vest","sequence":"first","affiliation":[]},{"given":"Sean","family":"Atsatt","sequence":"additional","affiliation":[]},{"given":"Mike","family":"Hutton","sequence":"additional","affiliation":[]}],"member":"263","event":{"name":"2014 IEEE Hot Chips 26 Symposium (HCS)","start":{"date-parts":[[2014,8,10]]},"location":"Cupertino, CA, USA","end":{"date-parts":[[2014,8,12]]}},"container-title":["2014 IEEE Hot Chips 26 Symposium (HCS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7470194\/7478793\/07478818.pdf?arnumber=7478818","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,17]],"date-time":"2017-03-17T16:16:08Z","timestamp":1489767368000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7478818\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,8]]},"references-count":0,"URL":"https:\/\/doi.org\/10.1109\/hotchips.2014.7478818","relation":{},"subject":[],"published":{"date-parts":[[2014,8]]}}}