{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T11:02:05Z","timestamp":1742382125254},"reference-count":29,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/hpca.2003.1183528","type":"proceedings-article","created":{"date-parts":[[2003,8,27]],"date-time":"2003-08-27T15:38:00Z","timestamp":1061998680000},"page":"103-112","source":"Crossref","is-referenced-by-count":28,"title":["Power-aware control speculation through selective throttling"],"prefix":"10.1109","author":[{"given":"J.L.","family":"Aragon","sequence":"first","affiliation":[]},{"given":"J.","family":"Gonzalez","sequence":"additional","affiliation":[]},{"given":"A.","family":"Gonzalez","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"crossref","DOI":"10.1109\/PACT.1996.554029","article-title":"Improving Branch Prediction Accuracy by Reducing Pattern History Table Interference","author":"chang","year":"1996","journal-title":"Proc of the Int Conf on Parallel Architectures and Compilation Techniques"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2001.937452"},{"key":"ref12","article-title":"Pentium 4 (Partially) Previewed","author":"glaskowsky","year":"2000","journal-title":"Microprocessor Report"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/4.535411"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1998.694768"},{"key":"ref15","article-title":"Selective Dual Path Execution","author":"heil","year":"1997","journal-title":"Technical Report"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1996.566457"},{"key":"ref17","article-title":"The Filter Cache: An Energy Efficient Memory Structure","author":"johnson","year":"2001","journal-title":"Proc of the Int Symp on Microarchitecture"},{"key":"ref18","article-title":"Analytical Energy Dissipation Models for Low Power Caches","author":"kamble","year":"1997","journal-title":"Proc of the Int Symp on Low Power Electronics and Design"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1998.694785"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1998.694778"},{"key":"ref4","doi-asserted-by":"crossref","DOI":"10.1145\/280756.295115","article-title":"Power and Performance Trade-Offs using Various Caching Strategies","author":"bahar","year":"1998","journal-title":"Proc of the Int Symp on Low Power Electronics and Design"},{"key":"ref27","first-page":"95","article-title":"Energy-driven integrated hardware-software optimizations using SimplePower","author":"vijaykrishnan","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/514191.514223"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/383082.383088"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/123465.123475"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2001.937451"},{"key":"ref8","first-page":"83","article-title":"Wattch: a framework for architectural-level power analysis and optimizations","author":"brooks","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1999.744314"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-45307-5_19"},{"key":"ref9","article-title":"Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors","author":"brooks","year":"2000","journal-title":"IEEE Micro"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1998.694788"},{"key":"ref20","article-title":"IBM's Power4 Unveiling Continues","author":"krewell","year":"2000","journal-title":"Microprocessor Report"},{"key":"ref22","article-title":"Combining Branch Predictors","author":"mcfarling","year":"1993","journal-title":"Tech Report #TN-36"},{"key":"ref21","doi-asserted-by":"crossref","DOI":"10.1145\/279361.279377","article-title":"Pipeline Gating: Speculation Control for Energy Reduction","author":"manne","year":"1998","journal-title":"Proc of the Int Symp on Computer Architecture"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2002.995713"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1997.604689"},{"key":"ref26","first-page":"41","article-title":"Shrinking Devices Put the Squeeze on System Packaging","author":"small","year":"1994"},{"key":"ref25","article-title":"Reducing Power with Dynamic Critical Path Information","author":"seng","year":"2001","journal-title":"Proc of the Int Symp on Microarchitecture"}],"event":{"name":"Ninth International Symposium on High-Performance Computer-Architecture. HPCA-9 2003","acronym":"HPCA-03","location":"Anaheim, CA, USA"},"container-title":["The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8433\/26557\/01183528.pdf?arnumber=1183528","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T00:09:00Z","timestamp":1497571740000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1183528\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":29,"URL":"https:\/\/doi.org\/10.1109\/hpca.2003.1183528","relation":{},"subject":[]}}