{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T15:29:43Z","timestamp":1742398183442},"reference-count":22,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/hpca.2006.1598121","type":"proceedings-article","created":{"date-parts":[[2006,3,21]],"date-time":"2006-03-21T17:46:16Z","timestamp":1142963176000},"page":"147-156","source":"Crossref","is-referenced-by-count":17,"title":["Increasing the Cache Efficiency by Eliminating Noise"],"prefix":"10.1109","author":[{"given":"P.","family":"Pujara","sequence":"first","affiliation":[]},{"given":"A.","family":"Aggarwal","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","article-title":"The span cache: Software controlled tag checks and cache line size","author":"witchel","year":"2001","journal-title":"Proc ISCA-28"},{"key":"22","article-title":"CACTI 3.0: An integrated cache timing, power, and area model","author":"shivakumar","year":"2002","journal-title":"Technical Report DEC Western Lab"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1987.5009537"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1145\/305138.305188"},{"key":"15","article-title":"The performance impact of block sizes and fetch strategies","author":"przybylski","year":"1993","journal-title":"Proc ISCA-20"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1994.288133"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1988.5210"},{"journal-title":"Compiler-directed Cache Line Size Adaptivity","year":"2000","author":"nicolaescu","key":"14"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645797"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1998.694794"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2004.10010"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1145\/268806.268810"},{"key":"20","article-title":"Energy benefits of a configurable line size cache for embedded systems","author":"zhang","year":"2003","journal-title":"Proc Int Symp VLSI"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1145\/232973.232983"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1999.765939"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1997.604734"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1145\/800015.808178"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1145\/263580.263631"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1145\/139669.139725"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253197"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1999.744366"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1995.476814"}],"event":{"name":"The Twelfth International Symposium on High-Performance Computer Architecture, 2006.","location":"Austin, Texas"},"container-title":["The Twelfth International Symposium on High-Performance Computer Architecture, 2006."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/10647\/33614\/01598121.pdf?arnumber=1598121","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,14]],"date-time":"2017-03-14T23:38:53Z","timestamp":1489534733000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1598121\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/hpca.2006.1598121","relation":{},"subject":[]}}