{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,14]],"date-time":"2024-09-14T14:23:52Z","timestamp":1726323832760},"reference-count":28,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/hpca.2006.1598133","type":"proceedings-article","created":{"date-parts":[[2006,3,21]],"date-time":"2006-03-21T22:46:16Z","timestamp":1142981176000},"source":"Crossref","is-referenced-by-count":9,"title":["Software-Hardware Cooperative Memory Disambiguation"],"prefix":"10.1109","author":[{"given":"R.","family":"Huang","sequence":"first","affiliation":[]},{"given":"A.","family":"Garg","sequence":"additional","affiliation":[]},{"given":"M.","family":"Huang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2000.824359"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1997.604684"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645814"},{"key":"15","article-title":"The technology behind crusoe?processors","author":"klaiber","year":"2000","journal-title":"Technical Report"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003562"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1994.288149"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1007\/BF01205185"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.46"},{"key":"12","article-title":"Implementing software-hardware cooperative memory disambiguation","author":"garg","year":"2005","journal-title":"Technical Report"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253245"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1002\/1097-024X(200101)31:1<67::AID-SPE357>3.0.CO;2-A"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1145\/125826.125848"},{"key":"23","article-title":"A high-bandwidth load-store unit for single- and multi- threaded processors","author":"roth","year":"2004","journal-title":"Technical Report (CIS)"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.48"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253244"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1147\/rd.461.0005"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.47"},{"key":"28","first-page":"124","article-title":"Direct addressed caches for reduced power consumption","author":"witchel","year":"2001","journal-title":"International Symposium on Microarchitecture"},{"key":"3","first-page":"245","article-title":"Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures","author":"balasubramonian","year":"2000","journal-title":"International Symposium on Microarchitecture"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253246"},{"key":"10","year":"2000","journal-title":"Alpha 21264\/EV6 Microprocessor Hardware Reference Manual"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253196"},{"key":"7","doi-asserted-by":"crossref","first-page":"90","DOI":"10.1145\/1028176.1006709","article-title":"Memory ordering: A value-based approach","author":"cain","year":"2004","journal-title":"International Symposium on Computer Architecture"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1145\/268806.268810"},{"key":"5","first-page":"83","article-title":"Wattch: a framework for architectural-level power analysis and optimizations","author":"brooks","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"4","article-title":"Decomposing the load-store queue by function for power reduction and scalability","author":"baugh","year":"2004","journal-title":"Watson Conference on Interaction between Architecture Circuits and Compilers"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1998.694770"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/40.671403"}],"event":{"name":"The Twelfth International Symposium on High-Performance Computer Architecture, 2006.","location":"Austin, Texas"},"container-title":["The Twelfth International Symposium on High-Performance Computer Architecture, 2006."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/10647\/33614\/01598133.pdf?arnumber=1598133","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,17]],"date-time":"2017-06-17T03:59:23Z","timestamp":1497671963000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1598133\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":28,"URL":"https:\/\/doi.org\/10.1109\/hpca.2006.1598133","relation":{},"subject":[]}}