{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T10:33:00Z","timestamp":1742380380600,"version":"3.28.0"},"reference-count":42,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/hpca.2006.1598137","type":"proceedings-article","created":{"date-parts":[[2006,3,21]],"date-time":"2006-03-21T17:46:16Z","timestamp":1142963176000},"page":"293-304","source":"Crossref","is-referenced-by-count":10,"title":["Efficient Instruction Schedulers for SMT Processors"],"prefix":"10.1109","author":[{"given":"J.J.","family":"Sharkey","sequence":"first","affiliation":[]},{"given":"D.V.","family":"Ponomarev","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2004.10014"},{"key":"35","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2005.195481"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2001.937452"},{"key":"36","article-title":"Instruction recirculation: Reducing power and delay of the dynamic scheduling logic","author":"sharkey","year":"2005","journal-title":"Proc ACM\/IEEE Euro-par Conference"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/2.869367"},{"key":"33","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2004.9"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003560"},{"key":"34","doi-asserted-by":"publisher","DOI":"10.1007\/11574859_2"},{"key":"16","doi-asserted-by":"crossref","DOI":"10.1145\/871656.859647","article-title":"Cyclone: A broadcast-free dynamic instruction scheduler with selective replay","author":"ernst","year":"2003","journal-title":"Proc International Symposium on Computer Architecture (ISCA)"},{"key":"39","doi-asserted-by":"crossref","DOI":"10.1109\/MICRO.2000.898058","article-title":"On pipelining dynamic instruction scheduling logic","author":"stark","year":"2000","journal-title":"Proc Int Symp Microarch (MICRO)"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2004.10016"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2003.1183522"},{"key":"37","article-title":"M-sim: A flexible, multi-threaded simulation environment","volume":"cs tr 5 dp1","author":"sharkey","year":"2005","journal-title":"Tech Report"},{"key":"11","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-540-39707-6_6","article-title":"Improving memory latency aware fetch policies for SMT processors","author":"cazorla","year":"2003","journal-title":"Proc Int l Symp High Performance Computing"},{"key":"38","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605403"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2004.10008"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253202"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1145\/566408.566456"},{"key":"42","doi-asserted-by":"crossref","first-page":"392","DOI":"10.1109\/ISCA.1995.524578","article-title":"Simultaneous multithreading: Maximizing on-chip parallelism","author":"tullsen","year":"1995","journal-title":"Proceedings 22nd Annual International Symposium on Computer Architecture ISCA"},{"key":"41","doi-asserted-by":"publisher","DOI":"10.1145\/232973.232993"},{"key":"40","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2001.991129"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1145\/859622.859623"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003562"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1145\/1006209.1006240"},{"key":"25","article-title":"Balancing throughput and fairness in SMT processors","author":"luo","year":"2001","journal-title":"Proc IEEE Int l Symp Performance Analysis of Systems and Software"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2001.903249"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1145\/384286.264201"},{"key":"28","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003589"},{"key":"29","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2001.991108"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2002.1176236"},{"key":"2","article-title":"Early stage definition of LPX: A low power issue-execute processor","author":"bose","year":"2002","journal-title":"Proc Workshop on Power-Aware Computer Systems"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.17"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2004.10013"},{"key":"30","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.814321"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859636"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1145\/368122.368807"},{"key":"32","article-title":"The impact of resource partitioning on SMT processors","author":"raasch","year":"2003","journal-title":"Proc PACT"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1145\/268806.268810"},{"key":"31","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2004.29"},{"key":"4","article-title":"Select-free instruction scheduling logic","author":"brown","year":"2001","journal-title":"Proc Int Symp Microarch (MICRO)"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1145\/377792.377854"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1145\/335231.335263"}],"event":{"name":"The Twelfth International Symposium on High-Performance Computer Architecture, 2006.","location":"Austin, Texas"},"container-title":["The Twelfth International Symposium on High-Performance Computer Architecture, 2006."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/10647\/33614\/01598137.pdf?arnumber=1598137","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,5,6]],"date-time":"2023-05-06T16:50:00Z","timestamp":1683391800000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1598137\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":42,"URL":"https:\/\/doi.org\/10.1109\/hpca.2006.1598137","relation":{},"subject":[]}}