{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,5]],"date-time":"2026-03-05T15:45:26Z","timestamp":1772725526584,"version":"3.50.1"},"reference-count":29,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,2]]},"DOI":"10.1109\/hpca.2009.4798239","type":"proceedings-article","created":{"date-parts":[[2009,3,10]],"date-time":"2009-03-10T13:52:31Z","timestamp":1236693151000},"page":"79-90","source":"Crossref","is-referenced-by-count":69,"title":["Practical off-chip meta-data for temporal memory streaming"],"prefix":"10.1109","author":[{"given":"Thomas F.","family":"Wenisch","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael","family":"Ferdman","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Anastasia","family":"Ailamaki","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Babak","family":"Falsafi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andreas","family":"Moshovos","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","article-title":"using cohort scheduling to enhance server performance","author":"larus","year":"2002","journal-title":"Proc of the USENIX Technical Conference"},{"key":"17","doi-asserted-by":"crossref","DOI":"10.1145\/325096.325162","article-title":"improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers","author":"jouppi","year":"1990","journal-title":"Proc International Symposium on Computer Architecture"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379259"},{"key":"15","article-title":"to share or not to share?","author":"johnson","year":"2007","journal-title":"Proc 22nd Conf Very Large Data Bases"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1997.604695"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2003.1183549"},{"key":"14","article-title":"exploring the design space of future cmps","author":"huh","year":"2001","journal-title":"Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques"},{"key":"11","article-title":"database servers on chip multiprocessors: limitations and opportunities","author":"hardavellas","year":"2007","journal-title":"CIDR Third Biennial Conference on Innovative Data Systems Research"},{"key":"12","doi-asserted-by":"crossref","DOI":"10.1145\/545214.545239","article-title":"timekeeping in the memory system: predicting and optimizing memory behavior","author":"hu","year":"2002","journal-title":"Proc International Symposium on Computer Architecture"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2004.10030"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1998.694761"},{"key":"22","doi-asserted-by":"crossref","DOI":"10.1109\/MICRO.2000.898057","article-title":"predictor-directed stream buffers","author":"sherwood","year":"2000","journal-title":"Proc 33rd Int'l Symp Microarchitecture (MICRO-33)"},{"key":"23","article-title":"using a userlevel memory thread for correlation prefetching","author":"yan","year":"2002","journal-title":"Proc International Symposium on Computer Architecture"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.38"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1997.569680"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2008.4636095"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.50"},{"key":"28","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2006.79"},{"key":"29","doi-asserted-by":"publisher","DOI":"10.1145\/335231.335247"},{"key":"3","year":"0"},{"key":"2","doi-asserted-by":"crossref","DOI":"10.1145\/1346281.1346301","article-title":"predictor virtualization","author":"burcea","year":"2008","journal-title":"Proc Int l Conf Architectural Support for Programming Languages and Operating Systems"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771774"},{"key":"1","year":"0"},{"key":"7","doi-asserted-by":"crossref","DOI":"10.1145\/1028176.1006708","article-title":"microarchitecture optimizations for exploiting memory-level parallelism","author":"chou","year":"2004","journal-title":"Proc International Symposium on Computer Architecture"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.39"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1145\/512553.512554"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1145\/378795.378840"},{"key":"9","doi-asserted-by":"crossref","DOI":"10.1109\/ISPASS.2007.363741","article-title":"last-touch correlated data streaming","author":"ferdman","year":"2007","journal-title":"IEEE International Symposium on Performance Analysis of Systems and Software"},{"key":"8","author":"cormen","year":"2001","journal-title":"Introduction to Algorithms"}],"event":{"name":"2009 IEEE 15th International Symposium on High Performance Computer Architecture (HPCA)","location":"Raleigh, NC, USA","start":{"date-parts":[[2009,2,14]]},"end":{"date-parts":[[2009,2,18]]}},"container-title":["2009 IEEE 15th International Symposium on High Performance Computer Architecture"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4795428\/4798227\/04798239.pdf?arnumber=4798239","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,3,11]],"date-time":"2024-03-11T08:32:13Z","timestamp":1710145933000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4798239\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,2]]},"references-count":29,"URL":"https:\/\/doi.org\/10.1109\/hpca.2009.4798239","relation":{},"subject":[],"published":{"date-parts":[[2009,2]]}}}