{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:53:29Z","timestamp":1759146809312},"reference-count":27,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,2]]},"DOI":"10.1109\/hpca.2009.4798256","type":"proceedings-article","created":{"date-parts":[[2009,3,10]],"date-time":"2009-03-10T13:52:31Z","timestamp":1236693151000},"page":"213-224","source":"Crossref","is-referenced-by-count":62,"title":["Blueshift: Designing processors for timing speculation from the ground up."],"prefix":"10.1109","author":[{"given":"Brian","family":"Greskamp","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lu","family":"Wan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ulya R.","family":"Karpuzcu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jeffrey J.","family":"Cook","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Josep","family":"Torrellas","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Deming","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Craig","family":"Zilles","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"year":"0","key":"19"},{"journal-title":"Architectural transplant","year":"2007","author":"smolens","key":"17"},{"key":"18","article-title":"reunion: complexityeffective multicore redundancy","author":"smolens","year":"2006","journal-title":"International Symposium on Microarchitecture"},{"year":"0","key":"15"},{"key":"16","doi-asserted-by":"crossref","DOI":"10.1145\/871656.859620","article-title":"temperature-aware microarchitecture","author":"skadron","year":"2003","journal-title":"International Symposium on Computer Architecture"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771810"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-9292-5_8"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.23"},{"journal-title":"SESC Simulator","year":"0","author":"renau","key":"12"},{"year":"0","key":"21"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379247"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.803949"},{"key":"23","article-title":"a 130nm generation logic technology featuring 70nm transistors, dual vt transistors and 6 layers of cu interconnects","author":"tyagi","year":"2000","journal-title":"IEEE Electron Devices Meeting"},{"article-title":"achieving typical delays in synchronous systems via timing error toleration","year":"2000","author":"uht","key":"24"},{"key":"25","article-title":"x-pipe: an adaptive resilient microarchitecture for parameter variations","author":"vera","year":"2006","journal-title":"Workshop on Architectural Support for Gigascale Integration"},{"article-title":"hotleakage: a temperature-aware model of subthreshold and gate leakage for architects","year":"2003","author":"zhang","key":"26"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2003.1257137"},{"key":"3","first-page":"83","article-title":"Wattch: a framework for architectural-level power analysis and optimizations","author":"brooks","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"2","article-title":"opportunities and challenges for better than worst case design","author":"austin","year":"2005","journal-title":"Proc Asia and South Pacific Design Automation Conference"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/2.982916"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1999.809458"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/92.974895"},{"key":"6","doi-asserted-by":"crossref","DOI":"10.1109\/PACT.2007.4336213","article-title":"paceline: improving single-thread performance in nanoscale cmps through core overclocking","author":"greskamp","year":"2007","journal-title":"Proc Int Conf Parallel Architectures and Compilation Techniques"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253179"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/92.711317"},{"key":"9","article-title":"performance improvement with circuit-level speculation","author":"liu","year":"2000","journal-title":"International Symposium on Microarchitecture"},{"key":"8","article-title":"mapping for better than worst-case delays in lut-based fpga designs","author":"kong","year":"2008","journal-title":"International Symposium on Field Programmable Gate Arrays"}],"event":{"name":"2009 IEEE 15th International Symposium on High Performance Computer Architecture (HPCA)","start":{"date-parts":[[2009,2,14]]},"location":"Raleigh, NC, USA","end":{"date-parts":[[2009,2,18]]}},"container-title":["2009 IEEE 15th International Symposium on High Performance Computer Architecture"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4795428\/4798227\/04798256.pdf?arnumber=4798256","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,18]],"date-time":"2019-05-18T15:27:07Z","timestamp":1558193227000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4798256\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,2]]},"references-count":27,"URL":"https:\/\/doi.org\/10.1109\/hpca.2009.4798256","relation":{},"subject":[],"published":{"date-parts":[[2009,2]]}}}