{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T12:12:44Z","timestamp":1763467964711},"reference-count":21,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,1]]},"DOI":"10.1109\/hpca.2010.5416645","type":"proceedings-article","created":{"date-parts":[[2010,4,7]],"date-time":"2010-04-07T14:36:36Z","timestamp":1270650996000},"page":"1-11","source":"Crossref","is-referenced-by-count":179,"title":["Improving read performance of Phase Change Memories via Write Cancellation and Write Pausing"],"prefix":"10.1109","author":[{"given":"Moinuddin K.","family":"Qureshi","sequence":"first","affiliation":[]},{"given":"Michele M.","family":"Franceschini","sequence":"additional","affiliation":[]},{"given":"Luis A.","family":"Lastras-Montano","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","article-title":"Parallelism-aware batch scheduling: Enhancing both performance and fairness of shared dram systems","author":"mutlu","year":"2008","journal-title":"ISCA-35"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2007.4418973"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/781027.781076"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555760"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1147\/rd.524.0465"},{"key":"ref15","first-page":"128","article-title":"Memory access scheduling","author":"rixner","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/511334.511343"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798259"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1063\/1.365627"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555761"},{"journal-title":"Low Power Double Data Rate 2 (LPDDR2)","article-title":"JEDEC Solid State Technology Assoc","year":"2009","key":"ref4"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1147\/rd.524.0439"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555758"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.32"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2007.4418933"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2003.1250880"},{"key":"ref2","article-title":"The performance of PC solid-state disks (SSDs) as a function of bandwidth","author":"dirik","year":"2009","journal-title":"concurrency device architecture and system organization"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2006439"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.21"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1063\/1.348620"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555759"}],"event":{"name":"2010 IEEE 16th International Symposium on High Performance Computer Architecture (HPCA)","start":{"date-parts":[[2010,1,9]]},"location":"Bangalore","end":{"date-parts":[[2010,1,14]]}},"container-title":["HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5410726\/5416625\/05416645.pdf?arnumber=5416645","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,19]],"date-time":"2017-03-19T00:02:26Z","timestamp":1489881746000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5416645\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,1]]},"references-count":21,"URL":"https:\/\/doi.org\/10.1109\/hpca.2010.5416645","relation":{},"subject":[],"published":{"date-parts":[[2010,1]]}}}